Patch v1.0.1: Mailbox Lock resets to 1 with Caliptra ownership

Release_Notes.md

@@ -14,11 +14,24 @@ See the License for the specific language governing permissions and<BR>
 limitations under the License.*_<BR>
 
 # **Release Notes** #
-_*Last Update: 2024/01/18*_
+_*Last Update: 2024/01/30*_
 
-## Rev 1p0 ##
+## Rev 1p0 Patch (v1.0.1) ##
 
-### Rev 1p0 release date: 2024/01/18 ###
+### v1.0.1 release date: 2024/01/30 ###
+- Verification
+  - Updated validation firmware images to unlock the mailbox at startup
+  - Fixes for UVM SOC_IFC test sequences to unlock the mailbox and correctly
+    perform transaction checking and scoreboarding
+
+### Bug Fixes ###
+[MBOX] Fix mailbox lock to initialize to 1 out of reset
+
+## Previous Releases ##
+
+### Rev 1p0 ###
+
+#### Rev 1p0 release date: 2024/01/18 ####
 - Caliptra Hardware Specification: Markdown conversion
 - Caliptra Integration specification update with synthesis warnings and jtag tck requirement
 - Caliptra README updates to clarify test cases and running with VCS
@@ -33,11 +46,9 @@ _*Last Update: 2024/01/18*_
   - Remove TODO comments on caliptra_top ports
   - Remove JTAG IDCODE command from RISC-V processor
 
-### Bug Fixes ###
+#### Bug Fixes ####
 [MBOX] Fix ICCM Uncorrectable ECC error driving hw_error_non_fatal bit for LSU reads
 
-## Previous Releases ##
-
 ### Rev 1p0-rc1 ###
 
 #### Rev 1p0-rc1 release date: 2023/11/03 (1p0 version pending ROM release for official declaration) ###

src/integration/test_suites/libs/riscv_hw_if/crt0.s

@@ -57,6 +57,11 @@ _start:
     la t0, early_trap_vector
     csrw mtvec, t0
 
+    // Unlock the mailbox (force)
+    li t0, CLP_MBOX_CSR_MBOX_UNLOCK
+    li t1, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK
+    sw t1, 0(t0)
+
     // Copy .data from ROM (imem) to DCCM
     la t0, _data_lma_start
     la t1, _data_lma_end

src/integration/test_suites/smoke_test_sha_accel/smoke_test_sha_accel.s

@@ -39,6 +39,11 @@ _start:
     la t0, early_trap_vector
     csrw mtvec, t0
 
+    // Unlock the mailbox (force)
+    li t0, CLP_MBOX_CSR_MBOX_UNLOCK
+    li t1, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK
+    sw t1, 0(t0)
+
     // Init. the stack
     la sp, STACK
 

src/soc_ifc/rtl/mbox_csr.rdl

@@ -33,10 +33,14 @@ addrmap mbox_csr {
     // clear comes from mailbox control
     reg {
         name="Mailbox Lock";
-        desc="Mailbox lock register for mailbox access, reading 0 will set the lock
+        desc="Mailbox lock register for mailbox access, reading 0 will set the lock.
+        [br]Lock has a reset value of 1 (soc_has_lock resets to 0) indicating
+            Caliptra initially owns the lock. Caliptra microcontroller may perform
+            direct-mode accesses to the mailbox memory, but must unlock and
+            reacquire the lock before it is able to send any mailbox commands.
         [br]Caliptra Access: RO
         [br]SOC Access:      RO";
-        field {rset; sw=r; hw=r; hwclr=true; precedence=hw; swmod=true;} lock=0;
+        field {rset; sw=r; hw=r; hwclr=true; precedence=hw; swmod=true;} lock=1;
     } mbox_lock;
 
     // user register

src/soc_ifc/rtl/mbox_csr.sv

@@ -263,7 +263,7 @@ module mbox_csr (
     end
     always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
         if(~hwif_in.cptra_rst_b) begin
-            field_storage.mbox_lock.lock.value <= 'h0;
+            field_storage.mbox_lock.lock.value <= 'h1;
         end else if(field_combo.mbox_lock.lock.load_next) begin
             field_storage.mbox_lock.lock.value <= field_combo.mbox_lock.lock.next;
         end

src/soc_ifc/rtl/mbox_csr_uvm.sv

@@ -25,7 +25,7 @@ package mbox_csr_uvm;
 
         virtual function void build();
             this.lock = new("lock");
-            this.lock.configure(this, 1, 0, "RS", 1, 'h0, 1, 1, 0);
+            this.lock.configure(this, 1, 0, "RS", 1, 'h1, 1, 1, 0);
             if (has_coverage(UVM_CVR_REG_BITS)) begin
                 foreach(lock_bit_cg[bt]) lock_bit_cg[bt] = new();
             end

src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/src/soc_ifc_cmdline_test_sequence.svh

@@ -37,6 +37,7 @@ class soc_ifc_cmdline_test_sequence extends soc_ifc_bench_sequence_base;
   rand soc_ifc_env_bringup_sequence_t soc_ifc_env_bringup_seq;
   rand soc_ifc_env_cptra_rst_wait_sequence_t soc_ifc_env_cptra_rst_wait_seq;
   rand soc_ifc_env_cptra_init_interrupts_sequence_t soc_ifc_env_cptra_init_interrupts_seq;
+  rand soc_ifc_env_cptra_mbox_unlock_sequence_t soc_ifc_env_cptra_mbox_unlock_seq;
 
   function new(string name = "" );
     super.new(name);
@@ -55,6 +56,7 @@ class soc_ifc_cmdline_test_sequence extends soc_ifc_bench_sequence_base;
     soc_ifc_env_cptra_rst_wait_seq = soc_ifc_env_cptra_rst_wait_sequence_t::type_id::create("soc_ifc_env_cptra_rst_wait_seq");
 
     soc_ifc_env_cptra_init_interrupts_seq = soc_ifc_env_cptra_init_interrupts_sequence_t::type_id::create("soc_ifc_env_cptra_init_interrupts_seq");
+    soc_ifc_env_cptra_mbox_unlock_seq     = soc_ifc_env_cptra_mbox_unlock_sequence_t::type_id::create("soc_ifc_env_cptra_mbox_unlock_seq");
 
     soc_ifc_ctrl_agent_random_seq      = soc_ifc_ctrl_agent_random_seq_t::type_id::create("soc_ifc_ctrl_agent_random_seq");
     cptra_ctrl_agent_random_seq        = cptra_ctrl_agent_random_seq_t::type_id::create("cptra_ctrl_agent_random_seq");
@@ -66,6 +68,7 @@ class soc_ifc_cmdline_test_sequence extends soc_ifc_bench_sequence_base;
     soc_ifc_env_bringup_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_status_agent_responder_seq;
     soc_ifc_env_cptra_rst_wait_seq.cptra_status_agent_rsp_seq = cptra_status_agent_responder_seq;
     soc_ifc_env_cptra_init_interrupts_seq.cptra_status_agent_rsp_seq = cptra_status_agent_responder_seq;
+    soc_ifc_env_cptra_mbox_unlock_seq.cptra_status_agent_rsp_seq = cptra_status_agent_responder_seq;
 
     reg_model.reset();
     // Start RESPONDER sequences here
@@ -93,9 +96,30 @@ class soc_ifc_cmdline_test_sequence extends soc_ifc_bench_sequence_base;
     // Always initialize interrupts
     // TODO - if we make this random, we can test both interrupt-driven and
     // polling behavior
+    soc_ifc_env_cptra_rst_wait_seq = soc_ifc_env_cptra_rst_wait_sequence_t::type_id::create("soc_ifc_env_cptra_rst_wait_uc_seq");
+    soc_ifc_env_cptra_rst_wait_seq.cptra_status_agent_rsp_seq = cptra_status_agent_responder_seq;
+    soc_ifc_env_cptra_rst_wait_seq.wait_for_noncore_rst_assert   = 1'b0;
+    soc_ifc_env_cptra_rst_wait_seq.wait_for_core_rst_assert      = 1'b0;
+    soc_ifc_env_cptra_rst_wait_seq.wait_for_noncore_rst_deassert = 1'b0;
+    soc_ifc_env_cptra_rst_wait_seq.wait_for_core_rst_deassert    = 1'b1;
+    // Wait for Caliptra uC (Core) reset to be deasserted by SOC_IFC
+    soc_ifc_env_cptra_rst_wait_seq.start(top_configuration.vsqr);
+    `uvm_info("SOC_IFC_CMDLINE_TEST", "SOC_IFC observed uC reset deassertion", UVM_LOW)
     soc_ifc_env_cptra_init_interrupts_seq.start(top_configuration.vsqr);
     `uvm_info("SOC_IFC_CMDLINE_TEST", "Completed interrupt init", UVM_MEDIUM)
 
+    // Delaying before unlocking mailbox roughly simulates the delay before
+    // the ROM can get around to doing the unlock
+    fork
+        begin: DELAY_THEN_MBOX_UNLOCK
+            int unsigned dly;
+            std::randomize(dly) with {dly > 0 ; dly < 256;};
+            soc_ifc_ctrl_agent_config.wait_for_num_clocks(dly);
+            soc_ifc_env_cptra_mbox_unlock_seq.start(top_configuration.vsqr);
+            `uvm_info("SOC_IFC_CMDLINE_TEST", "Completed mailbox unlock", UVM_MEDIUM)
+        end
+    join_none
+
     // Run cmdline provided env sequences
     clp = uvm_cmdline_processor::get_inst();
     if (!clp.get_arg_values("+CLP_SEQ=", seq_names))