Update VeeR codebase

Signed-off-by: Maciej Kurc <[email protected]>
chipsalliance · May 26, 2023 · 786d57c · 786d57c
1 parent 02f97ac
commit 786d57c
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Showing 5 changed files with 25 additions and 13 deletions.
diff --git a/src/integration/rtl/caliptra_top.sv b/src/integration/rtl/caliptra_top.sv
@@ -505,6 +505,7 @@ el2_veer_wrapper rvtop (
     .soft_int               (soft_int),
     .core_id                ('0),
     .scan_mode              ( cptra_scan_mode_Latched ), // To enable scan mode
+    .scan_rst_l             ( 1'b1 ),
     .mbist_mode             ( 1'b0 )        // to enable mbist
 
 );

diff --git a/src/riscv_core/veer_el2/rtl/el2_veer.sv b/src/riscv_core/veer_el2/rtl/el2_veer.sv
@@ -32,7 +32,7 @@ import el2_pkg::*;
    input logic [31:1]           rst_vec,
    input logic                  nmi_int,
    input logic [31:1]           nmi_vec,
-   output logic                 core_rst_l,   // This is "rst_l | dbg_rst_l"
+   output logic                 core_rst_l,   // This is "rst_l & (scan_rst_l | scan_mode)"
 
    output logic                 active_l2clk,
    output logic                 free_l2clk,
@@ -380,7 +380,8 @@ import el2_pkg::*;
    input logic [pt.PIC_TOTAL_INT:1]           extintsrc_req,
    input logic                   timer_int,
    input logic                   soft_int,
-   input logic                   scan_mode
+   input logic                   scan_mode,
+   input logic                   scan_rst_l
 );
 
 
@@ -856,7 +857,7 @@ import el2_pkg::*;
 
    // -----------------   DEBUG END -----------------------------
 
-   assign core_rst_l = rst_l & (dbg_core_rst_l | scan_mode);
+   assign core_rst_l = rst_l & (scan_rst_l | scan_mode);
    // fetch
    el2_ifu #(.pt(pt)) ifu (
                             .clk(active_l2clk),

diff --git a/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv b/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv
@@ -335,6 +335,7 @@ import soc_ifc_pkg::*;
    input logic                             i_cpu_run_req, // Async restart req to CPU
    output logic                            o_cpu_run_ack, // Core response to run req
    input logic                             scan_mode,     // To enable scan mode
+   input logic                             scan_rst_l,
    input logic                             mbist_mode     // to enable mbist
 );
 

diff --git a/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv b/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv
@@ -291,7 +291,7 @@ endmodule
 // special power flop for predict packet
 // format: { LEFT, RIGHT==31 }
 // LEFT # of bits will be done with rvdffe; RIGHT is enabled by LEFT[LSB] & en
-module rvdffppe #( parameter WIDTH=32 )
+module rvdffppe #( parameter integer WIDTH = 39 )
    (
      input  logic [WIDTH-1:0] din,
      input  logic             clk,
@@ -301,13 +301,13 @@ module rvdffppe #( parameter WIDTH=32 )
      output logic [WIDTH-1:0] dout
      );
 
-   localparam RIGHT = 31;
-   localparam LEFT = WIDTH - RIGHT;
+   localparam integer RIGHT = 31;
+   localparam integer LEFT  = WIDTH - RIGHT;
 
-   localparam LMSB = WIDTH-1;
-   localparam LLSB = LMSB-LEFT+1;
-   localparam RMSB = LLSB-1;
-   localparam RLSB = LLSB-RIGHT;
+   localparam integer LMSB  = WIDTH-1;
+   localparam integer LLSB  = LMSB-LEFT+1;
+   localparam integer RMSB  = LLSB-1;
+   localparam integer RLSB  = LLSB-RIGHT;
 
 
 `ifndef RV_PHYSICAL
@@ -748,7 +748,7 @@ module rvecc_decode_64  (
 
  endmodule // rvecc_decode_64
 
-
+`ifndef TECH_SPECIFIC_EC_RV_ICG
 module `TEC_RV_ICG
   (
    input logic SE, EN, CK,
@@ -773,6 +773,7 @@ module `TEC_RV_ICG
    assign Q = CK & en_ff;
 
 endmodule
+`endif
 
 `ifndef RV_FPGA_OPTIMIZE
 module rvclkhdr
@@ -786,7 +787,11 @@ module rvclkhdr
    logic   SE;
    assign       SE = 0;
 
+`ifdef TECH_SPECIFIC_EC_RV_ICG
+   `USER_EC_RV_ICG clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));
+`else
    `TEC_RV_ICG clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));
+`endif
 
 endmodule // rvclkhdr
 `endif
@@ -805,7 +810,11 @@ module rvoclkhdr
 `ifdef RV_FPGA_OPTIMIZE
    assign l1clk = clk;
 `else
-   `TEC_RV_ICG clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));
+   `ifdef TECH_SPECIFIC_EC_RV_ICG
+      `USER_EC_RV_ICG clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));
+   `else
+      `TEC_RV_ICG clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));
+    `endif
 `endif
 
 endmodule

diff --git a/src/riscv_core/veer_el2/tb/dasm.svi b/src/riscv_core/veer_el2/tb/dasm.svi
@@ -305,7 +305,7 @@ string mn;
     imm = opcode[24:20];
     case(opcode[14:12])
     1: mn = "slli";
-    5: mn = opcode[30] ? "srli": "srai";
+    5: mn = opcode[30] ? "srai": "srli";
     endcase
 
     return $sformatf("%s    %s,%s,%0d", mn, abi_reg[opcode[11:7]], abi_reg[opcode[19:15]], imm);