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SHA256 lint fixes (#466)
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* Lint fixes

* Added a comment for digest signal modification made for wntz op

* Remove redundant case

* Change casez to case

* Avoid mixing logical and bitwise operators

* Reset intr var so test can progress

* Clear intr variable inside wait function

* Remove hardcoding in generic wait function

* Add args to regular sha256 test

* Revert prev change and add error flow in test, update sva to check for regular sha as well

---------

Co-authored-by: Kiran Upadhyayula <[email protected]>
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@upadhyayulakiran
upadhyayulakiran and Kiran Upadhyayula authored Mar 19, 2024
1 parent 50c914f commit 612ea2e
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Showing 5 changed files with 101 additions and 25 deletions.
4 changes: 2 additions & 2 deletions src/integration/asserts/caliptra_top_sva.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -576,9 +576,9 @@ module caliptra_top_sva
// SVA for LMS WNTZ accelerator
wntz_mode: assert property (
@(posedge `SVA_RDC_CLK)
`SHA256_PATH.wntz_mode |-> (`SHA256_PATH.init_reg) & (!`SHA256_PATH.next_reg)
`SHA256_PATH.init_reg |-> !`SHA256_PATH.next_reg
)
else $display("SVA ERROR: WNTZ mode is not valid without INIT!");
else $display("SVA ERROR: SHA256 operation is not valid with INIT and NEXT asserted in the same cycle!");

// Bus IDLE on Firmware Update Reset
fw_upd_rst_doe_idle: assert property (@(posedge `SVA_RDC_CLK) `CPTRA_FW_UPD_RST_WINDOW |-> !`DOE_REG_PATH.s_cpuif_req)
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57 changes: 50 additions & 7 deletions src/integration/test_suites/libs/sha256/sha256.c
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Expand Up @@ -20,17 +20,21 @@

extern volatile caliptra_intr_received_s cptra_intr_rcv;

void wait_for_sha256_intr(){
void wait_for_sha256_intr(uint32_t notif, uint32_t error){
printf("SHA256 flow in progress...\n");
while((cptra_intr_rcv.sha256_error == 0) & (cptra_intr_rcv.sha256_notif == 0)){
while(((cptra_intr_rcv.sha256_error & error) != error) || ((cptra_intr_rcv.sha256_notif & notif) != notif)){
__asm__ volatile ("wfi"); // "Wait for interrupt"
// Sleep during SHA256 operation to allow ISR to execute and show idle time in sims
for (uint16_t slp = 0; slp < 100; slp++) {
__asm__ volatile ("nop"); // Sleep loop as "nop"
}
};
//printf("Received SHA256 error intr with status = %d\n", cptra_intr_rcv.sha256_error);
printf("Received SHA256 notif intr with status = %d\n", cptra_intr_rcv.sha256_notif);
if (error)
printf("Received SHA256 err intr with status = %d\n", cptra_intr_rcv.sha256_error);
else
printf("Received SHA256 notif intr with status = %d\n", cptra_intr_rcv.sha256_notif);
cptra_intr_rcv.sha256_notif &= ~notif;
cptra_intr_rcv.sha256_error &= ~error;
}

void sha256_zeroize(){
Expand Down Expand Up @@ -63,8 +67,7 @@ void sha256_flow(sha256_io block, uint8_t mode, uint8_t wntz_mode, uint8_t wntz_
((wntz_n << SHA256_REG_SHA256_CTRL_WNTZ_N_MODE_LOW) & SHA256_REG_SHA256_CTRL_WNTZ_N_MODE_MASK));

// wait for SHA to be valid
wait_for_sha256_intr();

wait_for_sha256_intr(SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK, 0);
reg_ptr = (uint32_t *) CLP_SHA256_REG_SHA256_DIGEST_0;
printf("Load DIGEST data from SHA256\n");
offset = 0;
Expand All @@ -83,6 +86,46 @@ void sha256_flow(sha256_io block, uint8_t mode, uint8_t wntz_mode, uint8_t wntz_

}

void sha256_error_flow(sha256_io block, uint8_t mode, uint8_t next, uint8_t wntz_mode, uint8_t wntz_w, uint8_t wntz_n, sha256_io digest, uint32_t error) {
volatile uint32_t * reg_ptr;
uint8_t offset;
uint8_t fail_cmd = 0x1;
uint32_t sha256_digest [8];

// wait for SHA to be ready
while((lsu_read_32(CLP_SHA256_REG_SHA256_STATUS) & SHA256_REG_SHA256_STATUS_READY_MASK) == 0);

// Write SHA256 block
reg_ptr = (uint32_t*) CLP_SHA256_REG_SHA256_BLOCK_0;
offset = 0;
while (reg_ptr <= (uint32_t*) CLP_SHA256_REG_SHA256_BLOCK_15) {
*reg_ptr++ = block.data[offset++];
}

// init and next triggers error1 bit. Check to make sure correct error arg is given
if (next & (error == SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_MASK)) {
printf("Error1 is expected when init and next are asserted at the same time. Check args given to sha256_error_flow()\n");
printf("%c", fail_cmd);
}
else if (~next & (error == SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR1_STS_MASK)) {
printf("Error0 is expected for invalid wntz_mode or w. Check args given to sha256_error_flow()\n");
printf("%c", fail_cmd);
}

// Enable SHA256 core
VPRINTF(LOW, "Enable SHA256\n");
lsu_write_32(CLP_SHA256_REG_SHA256_CTRL, SHA256_REG_SHA256_CTRL_INIT_MASK |
((next << SHA256_REG_SHA256_CTRL_NEXT_LOW) & SHA256_REG_SHA256_CTRL_NEXT_MASK) |
((mode << SHA256_REG_SHA256_CTRL_MODE_LOW) & SHA256_REG_SHA256_CTRL_MODE_MASK) |
((wntz_mode << SHA256_REG_SHA256_CTRL_WNTZ_MODE_LOW) & SHA256_REG_SHA256_CTRL_WNTZ_MODE_MASK) |
((wntz_w << SHA256_REG_SHA256_CTRL_WNTZ_W_LOW) & SHA256_REG_SHA256_CTRL_WNTZ_W_MASK) |
((wntz_n << SHA256_REG_SHA256_CTRL_WNTZ_N_MODE_LOW) & SHA256_REG_SHA256_CTRL_WNTZ_N_MODE_MASK));

// wait for SHA to trig error
wait_for_sha256_intr(0, error);

}

void sha256_flow_wntz_rand(uint8_t mode) {
// wait for SHA to be ready
while((lsu_read_32(CLP_SHA256_REG_SHA256_STATUS) & SHA256_REG_SHA256_STATUS_READY_MASK) == 0);
Expand All @@ -96,5 +139,5 @@ void sha256_flow_wntz_rand(uint8_t mode) {
// ((wntz_n << SHA256_REG_SHA256_CTRL_WNTZ_N_MODE_LOW) & SHA256_REG_SHA256_CTRL_WNTZ_N_MODE_MASK));

// wait for SHA to be valid
wait_for_sha256_intr();
wait_for_sha256_intr(SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK, 0);
}
1 change: 1 addition & 0 deletions src/integration/test_suites/libs/sha256/sha256.h
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Expand Up @@ -27,6 +27,7 @@ typedef struct {

void sha256_zeroize();
void sha256_flow(sha256_io block, uint8_t mode, uint8_t wntz_mode, uint8_t wntz_w, uint8_t wntz_n, sha256_io digest);
void sha256_error_flow(sha256_io block, uint8_t mode, uint8_t next, uint8_t wntz_mode, uint8_t wntz_w, uint8_t wntz_n, sha256_io digest, uint32_t error);
void sha256_flow_wntz_rand(uint8_t mode);

#endif
35 changes: 35 additions & 0 deletions src/integration/test_suites/smoke_test_sha256_wntz/smoke_test_sha256_wntz.c
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Expand Up @@ -255,6 +255,41 @@ void main() {
sha256_flow(sha256_block, SHA256_MODE_SHA_256, 1, 8, 0, sha256_digest);
sha256_zeroize();

//WNTZ errors

//Invalid w
sha256_digest.data_size = 8;
for (int i = 0; i < sha256_digest.data_size; i++)
sha256_digest.data[i] = expected_wntz_digest_w8_192[i];
// sha256_flow(sha256_block, SHA256_MODE_SHA_256, 1, 3, 0, sha256_digest);
sha256_error_flow(sha256_block, SHA256_MODE_SHA_256, 0, 1, 3, 0, sha256_digest, SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_MASK);
sha256_zeroize();

//Invalid mode
sha256_digest.data_size = 8;
for (int i = 0; i < sha256_digest.data_size; i++)
sha256_digest.data[i] = expected_wntz_digest_w8_192[i];
// sha256_flow(sha256_block, SHA256_MODE_SHA_224, 1, 8, 0, sha256_digest);
sha256_error_flow(sha256_block, SHA256_MODE_SHA_224, 0, 1, 8, 0, sha256_digest, SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_MASK);
sha256_zeroize();

//SVA in place to check init and next in same cycle
// //Invalid wntz op (init and next in same cycle)
// sha256_digest.data_size = 8;
// for (int i = 0; i < sha256_digest.data_size; i++)
// sha256_digest.data[i] = expected_wntz_digest_w8_192[i];
// // sha256_flow(sha256_block, SHA256_MODE_SHA_256, 1, 8, 0, sha256_digest);
// sha256_error_flow(sha256_block, SHA256_MODE_SHA_256, 1, 1, 4, 0, sha256_digest, SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR1_STS_MASK);
// sha256_zeroize();

// //Invalid regular sha op (init and next in same cycle)
// sha256_digest.data_size = 8;
// for (int i = 0; i < sha256_digest.data_size; i++)
// sha256_digest.data[i] = expected_wntz_digest_w8_192[i];
// // sha256_flow(sha256_block, SHA256_MODE_SHA_256, 0, 8, 0, sha256_digest);
// sha256_error_flow(sha256_block, SHA256_MODE_SHA_256, 1, 0, 0, 0, sha256_digest, SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR1_STS_MASK);
// sha256_zeroize();

// Write 0xff to STDOUT for TB to terminate test.
SEND_STDOUT_CTRL( 0xff);
while(1);
Expand Down
29 changes: 13 additions & 16 deletions src/sha256/rtl/sha256.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -100,7 +100,7 @@ module sha256
//----------------------------------------------------------------
wire core_ready;
logic [511 : 0] core_block;
wire [0:7][31:0] core_digest;
wire [0:7][31:0] core_digest; //Intentionally reverse ordered to prepare block input in wntz mode
wire core_digest_valid;
logic core_digest_valid_reg;

Expand All @@ -122,11 +122,11 @@ module sha256
logic core_init, core_next, core_mode;
logic wntz_init;
logic wntz_init_reg;
logic wntz_1st_blk, wntz_blk_done;
logic wntz_blk_done;
logic [7:0] wntz_iter, wntz_iter_reg;
logic [175: 0] wntz_prefix;

typedef enum logic [2:0] {WNTZ_IDLE, WNTZ_1ST, WNTZ_OTHERS} wntz_fsm_t;
typedef enum logic [1:0] {WNTZ_IDLE, WNTZ_1ST, WNTZ_OTHERS} wntz_fsm_t;
wntz_fsm_t wntz_fsm, wntz_fsm_next;


Expand Down Expand Up @@ -191,15 +191,14 @@ module sha256

//----------------------------------------------------------------
assign wntz_busy = (wntz_fsm != WNTZ_IDLE);
assign wntz_1st_blk = (wntz_fsm == WNTZ_1ST);
assign wntz_blk_done = core_digest_valid & ~core_digest_valid_reg;
assign wntz_w_invalid = wntz_busy & !(wntz_w_reg inside {'h1, 'h2, 'h4, 'h8});
assign wntz_mode_invalid = wntz_busy & !mode_reg;
assign wntz_j_invalid = wntz_mode && (wntz_j_init > wntz_iter);
assign invalid_sha_op = init_reg && next_reg; //Trigger an error when init and next are high in the same cycle
assign wntz_w_invalid = wntz_busy & ~(wntz_w_reg inside {'h1, 'h2, 'h4, 'h8});
assign wntz_mode_invalid = wntz_busy & ~mode_reg;
assign wntz_j_invalid = wntz_mode & (wntz_j_init > wntz_iter);
assign invalid_sha_op = init_reg & next_reg; //Trigger an error when init and next are high in the same cycle

always_comb begin
unique casez(wntz_w)
unique case(wntz_w)
8'h1: wntz_iter = 'd0; //2**w - 1 (-1) (1st iteration is considered separately)
8'h2: wntz_iter = 'd2;
8'h4: wntz_iter = 'd14;
Expand Down Expand Up @@ -316,24 +315,22 @@ module sha256
get_mask <= {8{32'hffff_ffff}};
end
else if (wntz_busy) begin
unique casez (wntz_n_mode_reg)
unique case (wntz_n_mode_reg)
0: get_mask <= {{6{32'hffff_ffff}}, {2{32'h0000_0000}}};
1: get_mask <= {8{32'hffff_ffff}};
default: get_mask <= {8{32'hffff_ffff}};
endcase
end
else begin
unique casez (mode_reg)
unique case (mode_reg)
0: get_mask <= {{7{32'hffff_ffff}}, {1{32'h0000_0000}}};
1: get_mask <= {8{32'hffff_ffff}};
default: get_mask <= {8{32'hffff_ffff}};
endcase
end
end

assign ready_flag = core_ready & !wntz_busy;
assign ready_flag = core_ready & ~wntz_busy;
assign ready_reg = ready_flag & ready_flag_reg;
assign valid_flag = core_digest_valid & !wntz_busy;
assign valid_flag = core_digest_valid & ~wntz_busy;
assign digest_valid_reg = valid_flag & valid_flag_reg;

always @ (posedge clk or negedge reset_n)
Expand Down Expand Up @@ -420,7 +417,7 @@ module sha256
assign hwif_in.sha256_ready = ready_reg;
assign hwif_in.reset_b = reset_n;
assign hwif_in.error_reset_b = cptra_pwrgood;
assign hwif_in.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.hwset = core_digest_valid & ~digest_valid_reg;
assign hwif_in.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.hwset = (~wntz_busy & core_digest_valid & ~digest_valid_reg);
assign hwif_in.intr_block_rf.error_internal_intr_r.error0_sts.hwset = wntz_w_invalid | wntz_mode_invalid | wntz_j_invalid;
assign hwif_in.intr_block_rf.error_internal_intr_r.error1_sts.hwset = invalid_sha_op;
assign hwif_in.intr_block_rf.error_internal_intr_r.error2_sts.hwset = 1'b0; // TODO
Expand Down

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