[RTL] Remove QSPI/UART and merge AXI module tweaks from FPGA testing (#…

…619)

* Increase fifo depth

* Excl. feature enabled through macro instead of param, to avoid large signal declarations

* Fix dv so it is not dependent upon axi rready directly

* Remove qspi/uart/i3c instances and references

* Regenerate file lists

* Remove accidentally committed build files

* Cleanup cptra_intr_rcv struct (and rm qspi/uart/i3c)

* Add missing cg tests and new sha512 restore test to nightly dir. regr

* More cptra_intr_rcv struct cleanup (C files)

* MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-demo-cleanup' with updated timestamp and hash after successful run

* Revision<->Version

* Checkout with submodules for PR checks

* Restamp repo with old timestamp -- test workflow

* Syntax fix

* Restamp again

* Full restamp

* Omit .git (which is a file, not dir, in submodules)

* MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-demo-cleanup' with updated timestamp and hash after successful run

* Update target indices

.github/scripts/license_header_check.sh

@@ -78,7 +78,7 @@ exclude_dir='{uvmf*,.git,cmark,caliptra_reg_html,caliptra_top_reg_html,sha256,sh
 exclude_suffix='*.{tcl,txt,js,htm,html,json,vf,yml,woff,rsp,rdl,bashrc,waiver,cfg,hex,rc,exe,pdf,png,hvp,svg,log}'
 exclude_regs='*_reg*.{sv,rdl}'
 exclude_csr='*_csr*.*'
-exclude_file='{sglint_waivers,pr_hash,pr_timestamp,.git-comodules,.gitignore,.gitmodules,spyglass_lint.policy,ascent.ctl,clp_mapfile,readme.md,README.md,SECURITY.md,c_sample.c,test_dilithium5}'
+exclude_file='{sglint_waivers,pr_hash,pr_timestamp,.git,.git-comodules,.gitignore,.gitmodules,spyglass_lint.policy,ascent.ctl,clp_mapfile,readme.md,README.md,SECURITY.md,c_sample.c,test_dilithium5}'
 apache_patn='Licensed under the Apache License\|Apache License, Version 2\.0 (the \"License\")'
 
 # Recursive find through repository with some major exclusions

.github/workflow_metadata/pr_hash

@@ -1 +1 @@
-6c8e7c3d77cadcbbf3b13e4f0f6853df60f57395826819dfbfda73a1a14f4533e5ca20c786cbb1b2535b771c4ebfa2b4
+426fad68287a654b7e3a594868725ab332e504264ad8bbac10778c144ee457056b1b323c81f86d149cefd24f1cd192d9

.github/workflow_metadata/pr_timestamp

@@ -1 +1 @@
-1730243083
+1730409602

.github/workflows/pre-run-check.yml

@@ -33,6 +33,7 @@ jobs:
         uses: actions/checkout@v4
         with:
             fetch-depth: 0
+            submodules: 'true'
       - name: Compare against target
         env:
             PR_OPENER:   ${{ github.event.pull_request.user.login }}
@@ -76,6 +77,7 @@ jobs:
         uses: actions/checkout@v4
         with:
             fetch-depth: 0
+            submodules: 'true'
 
       - name: Gen File List
         run: |
@@ -167,6 +169,9 @@ jobs:
     steps:
       - name: Checkout RTL repo
         uses: actions/checkout@v4
+        with:
+            fetch-depth: 0
+            submodules: 'true'
 
       - name: Run Script
         run: |
@@ -183,6 +188,7 @@ jobs:
         uses: actions/checkout@v4
         with:
             fetch-depth: 0
+            submodules: 'true'
 
       - name: Install peakrdl
         run: |

README.md

@@ -138,11 +138,9 @@ caliptra-rtl
 |   |-- sha256
 |   |-- sha512
 |   |-- sha512_masked
-|   |-- soc_ifc
-|   |-- spi_host
-|   `-- uart
+|   `-- soc_ifc
 |-- submodules
-    |-- adams-bridge
+    `-- adams-bridge
 `-- tools
     |-- README
     |-- scripts
@@ -188,27 +186,18 @@ Verilog file lists are generated via VCS and included in the config directory fo
     - NOTE: Users may wish to produce a run log by piping the make command to a tee command, e.g.:
         `make ... <args> ... | tee <path/to/run/folder>/vcs.log`
     - NOTE: The following macro values may be overridden to define the hardware configuration that is built. Default values in the Makefile are shown with each macro:
-      - CALIPTRA_INTERNAL_QSPI=1
-      - CALIPTRA_INTERNAL_UART=1
-      - CALIPTRA_INTERNAL_I3C=0
       - CALIPTRA_INTERNAL_TRNG=1
-      - E.g. `make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile CALIPTRA_INTERNAL_QSPI=0 CALIPTRA_INTERNAL_UART=0 CALIPTRA_INTERNAL_I3C=0 CALIPTRA_INTERNAL_TRNG=1 vcs`
+      - E.g. `make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile CALIPTRA_INTERNAL_TRNG=1 vcs`
 1. Remaining steps describe how to manually run the individual steps for a VCS simulation
 1. [OPTIONAL] By default, this run flow will use the RISC-V toolchain to compile test firmware (according to TESTNAME) into program.hex, iccm.hex, dccm.hex, and mailbox.hex. As a first pass, integrators may alternatively use the pre-built hexfiles for convenience (available for [iccm_lock](src/integration/test_suites/iccm_lock) test). To do this, copy [iccm_lock.hex](src/integration/test_suites/iccm_lock/iccm_lock.hex) to the run directory and rename to `program.hex`. [dccm.hex](src/integration/test_suites/iccm_lock/iccm_lock.hex) should also be copied to the run directory, as-is. Use `touch iccm.hex mailbox.hex` to create empty hex files, as these are unnecessary for `iccm_lock` test.
 1. Invoke `${CALIPTRA_ROOT}/tools/scripts/Makefile` with target 'program.hex' to produce SRAM initialization files from the firmware found in `src/integration/test_suites/${TESTNAME}`
     - E.g.: `make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile program.hex`
     - NOTE: TESTNAME may also be overridden in the makefile command line invocation, e.g. `make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile TESTNAME=iccm_lock program.hex`
     - NOTE: The following macro values must be overridden to match the value provided (later) during hardware compilation. The full L0 regression suite includes tests that will fail if the firmware and hardware configuration has a discrepancy. Default values in the Makefile are shown with each macro:
-      - CALIPTRA_INTERNAL_QSPI=1
-      - CALIPTRA_INTERNAL_UART=1
-      - CALIPTRA_INTERNAL_I3C=0
       - CALIPTRA_INTERNAL_TRNG=1
-      - E.g. `make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile CALIPTRA_INTERNAL_QSPI=0 CALIPTRA_INTERNAL_UART=0 CALIPTRA_INTERNAL_I3C=0 CALIPTRA_INTERNAL_TRNG=1 program.hex`
+      - E.g. `make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile CALIPTRA_INTERNAL_TRNG=1 program.hex`
 1. Compile complete project using `src/integration/config/caliptra_top_tb.vf` as a compilation target in VCS. When running the `vcs` command to generate simv, users should ensure that `caliptra_top_tb` is explicitly specified as the top-level component in their command to ensure this is the sole "top" that gets simulated.
     - NOTE: The following macro values must be defined (or omitted) to match the value provided during firmware compilation. The full L0 regression suite includes tests that will fail if the firmware and hardware configuration has a discrepancy.
-      - CALIPTRA_INTERNAL_QSPI
-      - CALIPTRA_INTERNAL_UART
-      - CALIPTRA_INTERNAL_I3C
       - CALIPTRA_INTERNAL_TRNG
 1. Copy the test generator scripts to the run output directory:
     - [src/ecc/tb/ecc_secp384r1.exe](src/ecc/tb/ecc_secp384r1.exe)

docs/CaliptraHardwareSpecification.md

@@ -2,8 +2,8 @@
 
 <p style="text-align: center;">Caliptra Hardware Specification</p>
 
-<p style="text-align: center;">Version 2.0</p>
-<p style="text-align: center;">Revision 0.8</p>
+<p style="text-align: center;">Revision 2.0</p>
+<p style="text-align: center;">Version 0.8</p>
 
 <div style="page-break-after: always"></div>
 
@@ -108,36 +108,36 @@ The following table shows the memory map address ranges for each of the IP block
 | PCR Vault                           | 4         | 8 KiB        | 0x1001_A000   | 0x1001_BFFF |
 | Data Vault                          | 5         | 8 KiB        | 0x1001_C000   | 0x1001_DFFF |
 | SHA512                              | 6         | 32 KiB       | 0x1002_0000   | 0x1002_7FFF |
-| SHA256                              | 13        | 32 KiB       | 0x1002_8000   | 0x1002_FFFF |
-| ML-DSA                              | 17        | 64 KiB       | 0x1003_0000   | 0x1003_FFFF |
+| SHA256                              | 10        | 32 KiB       | 0x1002_8000   | 0x1002_FFFF |
+| ML-DSA                              | 14        | 64 KiB       | 0x1003_0000   | 0x1003_FFFF |
 
 #### Peripherals subsystem
 
 The following table shows the memory map address ranges for each of the IP blocks in the peripherals’ subsystem.
 
 | IP/Peripheral | Target \# | Address size | Start address | End address |
 | :------------ | :-------- | :----------- | :------------ | :---------- |
-| CSRNG         | 15        | 4 KiB        | 0x2000_2000   | 0x2000_2FFF |
-| ENTROPY SRC   | 16        | 4 KiB        | 0x2000_3000   | 0x2000_3FFF |
+| CSRNG         | 12        | 4 KiB        | 0x2000_2000   | 0x2000_2FFF |
+| ENTROPY SRC   | 13        | 4 KiB        | 0x2000_3000   | 0x2000_3FFF |
 
 #### SoC interface subsystem
 
 The following table shows the memory map address ranges for each of the IP blocks in the SoC interface subsystem.
 
 | IP/Peripheral              | Target \# | Address size | Start address | End address |
 | :------------------------- | :-------- | :----------- | :------------ | :---------- |
-| Mailbox SRAM Direct Access | 10        | 128 KiB      | 0x3000_0000   | 0x3001_FFFF |
-| Mailbox CSR                | 10        | 4 KiB        | 0x3002_0000   | 0x3002_0FFF |
-| Mailbox                    | 10        | 64 KiB       | 0x3003_0000   | 0x3003_FFFF |
+| Mailbox SRAM Direct Access | 7         | 128 KiB      | 0x3000_0000   | 0x3001_FFFF |
+| Mailbox CSR                | 7         | 4 KiB        | 0x3002_0000   | 0x3002_0FFF |
+| Mailbox                    | 7         | 64 KiB       | 0x3003_0000   | 0x3003_FFFF |
 
 #### RISC-V core local memory blocks
 
 The following table shows the memory map address ranges for each of the local memory blocks that interface with RISC-V core.
 
 | IP/Peripheral   | Target \# | Address size | Start address | End address |
 | :-------------- | :-------- | :----------- | :------------ | :---------- |
-| ICCM0 (via DMA) | 12        | 128 KiB      | 0x4000_0000   | 0x4001_FFFF |
-| DCCM            | 11        | 128 KiB      | 0x5000_0000   | 0x5001_FFFF |
+| ICCM0 (via DMA) | 9         | 128 KiB      | 0x4000_0000   | 0x4001_FFFF |
+| DCCM            | 8         | 128 KiB      | 0x5000_0000   | 0x5001_FFFF |
 
 ### Interrupts
 

src/axi/rtl/axi_dma_ctrl.sv

@@ -81,7 +81,7 @@ import soc_ifc_pkg::*;
     // Localparams/Typedefs                    //
     // --------------------------------------- //
 
-    localparam FIFO_BC = 128; // depth in bytes
+    localparam FIFO_BC = 512; // depth in bytes
     localparam FIFO_BW = caliptra_prim_util_pkg::vbits((FIFO_BC/BC)+1); // width of a signal that reports FIFO slot consumption
 
     // Smaller of

src/axi/rtl/axi_sub.sv

@@ -66,12 +66,14 @@ module axi_sub import axi_pkg::*; #(
 );
 
     // Exclusive Access Signals
+    `ifdef CALIPTRA_AXI_SUB_EX_EN
     logic        [ID_NUM-1:0] ex_clr;
     logic        [ID_NUM-1:0] ex_active;
     struct packed {
         logic [AW-1:0] addr;
         logic [AW-1:0] addr_mask;
     } [ID_NUM-1:0] ex_ctx;
+    `endif
 
     //Read Subordinate INF
     logic          r_dv;
@@ -100,9 +102,8 @@ module axi_sub import axi_pkg::*; #(
         .AW   (AW   ),
         .DW   (DW   ),
         .UW   (UW   ),
-        .IW   (IW   ),
+        .IW   (IW   )
 
-        .EX_EN(EX_EN)
     ) i_axi_sub_wr (
         .clk  (clk  ),
         .rst_n(rst_n),
@@ -111,9 +112,11 @@ module axi_sub import axi_pkg::*; #(
         .s_axi_if(s_axi_w_if),
 
         // Exclusive Access Signals
+        `ifdef CALIPTRA_AXI_SUB_EX_EN
         .ex_clr   (ex_clr   ),
         .ex_active(ex_active),
         .ex_ctx   (ex_ctx   ),
+        `endif
 
         //COMPONENT INF
         .dv   (w_dv   ),
@@ -134,7 +137,6 @@ module axi_sub import axi_pkg::*; #(
         .UW(UW),
         .IW(IW),
 
-        .EX_EN(EX_EN),
         .C_LAT(C_LAT)
     ) i_axi_sub_rd (
         .clk  (clk  ),
@@ -144,9 +146,11 @@ module axi_sub import axi_pkg::*; #(
         .s_axi_if(s_axi_r_if),
 
         // Exclusive Access Signals
+        `ifdef CALIPTRA_AXI_SUB_EX_EN
         .ex_clr   (ex_clr   ),
         .ex_active(ex_active),
         .ex_ctx   (ex_ctx   ),
+        `endif
 
         //COMPONENT INF
         .dv   (r_dv   ),
@@ -166,7 +170,6 @@ module axi_sub import axi_pkg::*; #(
         .UW(UW),
         .IW(IW),
 
-        .EX_EN(EX_EN),
         .C_LAT(C_LAT)
     ) i_axi_sub_arb (
         .clk    (clk    ),

src/axi/rtl/axi_sub_arb.sv

@@ -31,7 +31,6 @@ module axi_sub_arb import axi_pkg::*; #(
     parameter IW = 1,          // ID Width
               ID_NUM = 1 << IW, // Don't override
 
-    parameter EX_EN = 0,   // Enable exclusive access tracking w/ AxLOCK
     parameter C_LAT = 0    // Component latency in clock cycles from (dv&&!hld) -> rdata
                            // Must be const per component
                            // For registers, typically 0