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[RTL] Remove QSPI/UART and merge AXI module tweaks from FPGA testing … #526

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[RTL] Remove QSPI/UART and merge AXI module tweaks from FPGA testing …

[RTL] Remove QSPI/UART and merge AXI module tweaks from FPGA testing … #526

Run time

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Job Run time
build_verilator
28s
build_openocd
5s
Run GDB debugging tests
19m 53s
Run OpenOCD debugging tests
8m 48s
29m 14s