[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/dec/el2_dec_gpr_ctl.sv:49:- logic [31:1] [31:0] gpr_out; // 31 x 32 bit GPRs design/dec/el2_dec_gpr_ctl.sv:50:- logic [31:1] [31:0] gpr_in; design/dec/el2_dec_gpr_ctl.sv:51:- logic [31:1] w0v,w1v,w2v; design/dec/el2_dec_gpr_ctl.sv:52:- logic [31:1] gpr_wr_en; design/dec/el2_dec_gpr_ctl.sv:49:+ logic [31:1][31:0] gpr_out; // 31 x 32 bit GPRs design/dec/el2_dec_gpr_ctl.sv:50:+ logic [31:1][31:0] gpr_in; design/dec/el2_dec_gpr_ctl.sv:51:+ logic [31:1] w0v, w1v, w2v; design/dec/el2_dec_gpr_ctl.sv:52:+ logic [31:1] gpr_wr_en;

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/dec/el2_dec_gpr_ctl.sv:68:- // GPR Write Enables design/dec/el2_dec_gpr_ctl.sv:69:- assign gpr_wr_en[31:1] = (w0v[31:1] | w1v[31:1] | w2v[31:1]); design/dec/el2_dec_gpr_ctl.sv:70:- for ( genvar j=1; j<32; j++ ) begin : gpr design/dec/el2_dec_gpr_ctl.sv:71:- rvdffe #(32) gprff (.*, .en(gpr_wr_en[j]), .din(gpr_in[j][31:0]), .dout(gpr_out[j][31:0])); design/dec/el2_dec_gpr_ctl.sv:72:- end : gpr design/dec/el2_dec_gpr_ctl.sv:73:- design/dec/el2_dec_gpr_ctl.sv:74:- // the read out design/dec/el2_dec_gpr_ctl.sv:75:- always_comb begin design/dec/el2_dec_gpr_ctl.sv:76:- rd0[31:0] = 32'b0; design/dec/el2_dec_gpr_ctl.sv:77:- rd1[31:0] = 32'b0; design/dec/el2_dec_gpr_ctl.sv:78:- w0v[31:1] = 31'b0; design/dec/el2_dec_gpr_ctl.sv:79:- w1v[31:1] = 31'b0; design/dec/el2_dec_gpr_ctl.sv:80:- w2v[31:1] = 31'b0; design/dec/el2_dec_gpr_ctl.sv:81:- gpr_in[31:1] = '0; design/dec/el2_dec_gpr_ctl.sv:82:- design/dec/el2_dec_gpr_ctl.sv:83:- // GPR Read logic design/dec/el2_dec_gpr_ctl.sv:84:- for (int j=1; j<32; j++ ) begin design/dec/el2_dec_gpr_ctl.sv:85:- rd0[31:0] |= ({32{(raddr0[4:0]== 5'(j))}} & gpr_out[j][31:0]); design/dec/el2_dec_gpr_ctl.sv:86:- rd1[31:0] |= ({32{(raddr1[4:0]== 5'(j))}} & gpr_out[j][31:0]); design/dec/el2_dec_gpr_ctl.sv:87:- end design/dec/el2_dec_gpr_ctl.sv:88:- design/dec/el2_dec_gpr_ctl.sv:89:- // GPR Write logic design/dec/el2_dec_gpr_ctl.sv:90:- for (int j=1; j<32; j++ ) begin design/dec/el2_dec_gpr_ctl.sv:91:- w0v[j] = wen0 & (waddr0[4:0]== 5'(j) ); design/dec/el2_dec_gpr_ctl.sv:92:- w1v[j] = wen1 & (waddr1[4:0]== 5'(j) ); design/dec/el2_dec_gpr_ctl.sv:93:- w2v[j] = wen2 & (waddr2[4:0]== 5'(j) ); design/dec/el2_dec_gpr_ctl.sv:94:- gpr_in[j] = ({32{w0v[j]}} & wd0[31:0]) | design/dec/el2_dec_gpr_ctl.sv:68:+ // GPR Write Enables design/dec/el2_dec_gpr_ctl.sv:69:+ assign gpr_wr_en[31:1] = (w0v[31:1] | w1v[31:1] | w2v[31:1]); design/dec/el2_dec_gpr_ctl.sv:70:+ for (genvar j = 1; j < 32; j++) begin : gpr design/dec/el2_dec_gpr_ctl.sv:71:+ rvdffe #(32) gprff ( design/dec/el2_dec_gpr_ctl.sv:72:+ .*, design/dec/el2_dec_gpr_ctl.sv:73:+ .en (gpr_wr_en[j]), design/dec/el2_dec_gpr_ctl.sv:74:+ .din (gpr_in[j][31:0]), design/dec/el2_dec_gpr_ctl.sv:75:+ .dout(gpr_out[j][31:0]) design/dec/el2_dec_gpr_ctl.sv:76:+ ); design/dec/el2_dec_gpr_ctl.sv:77:+ end : gpr design/dec/el2_dec_gpr_ctl.sv:78:+ design/dec/el2_dec_gpr_ctl.sv:79:+ // the read out design/dec/el2_dec_gpr_ctl.sv:80:+ always_comb begin design/dec/el2_dec_gpr_ctl.sv:81:+ rd0[31:0] = 32'b0; design/dec/el2_dec_gpr_ctl.sv:82:+ rd1[31:0] = 32'b0; design/dec/el2_dec_gpr_ctl.sv:83:+ w0v[31:1] = 31'b0; design/dec/el2_dec_gpr_ctl.sv:84:+ w1v[31:1] = 31'b0; design/dec/el2_dec_gpr_ctl.sv:85:+ w2v[31:1] = 31'b0; design/dec/el2_dec_gpr_ctl.sv:86:+ gpr_in[31:1] = '0; design/dec/el2_dec_gpr_ctl.sv:87:+ design/dec/el2_dec_gpr_ctl.sv:88:+ // GPR Read logic design/dec/el2_dec_gpr_ctl.sv:89:+ for (int j = 1; j < 32; j++) begin design/dec/el2_dec_gpr_ctl.sv:90:+ rd0[31:0] |= ({32{(raddr0[4:0] == 5'(j))}} & gpr_out[j][31:0]); design/dec/el2_dec_gpr_ctl.sv:91:+ rd1[31:0] |= ({32{(raddr1[4:0] == 5'(j))}} & gpr_out[j][31:0]); design/dec/el2_dec_gpr_ctl.sv:92:+ end design/dec/el2_dec_gpr_ctl.sv:93:+ design/dec/el2_dec_gpr_ctl.sv:94:+ // GPR Write logic design/dec/el2_dec_gpr_ctl.sv:95:+ for (int j = 1; j < 32; j++) begin design/dec/el2_dec_gpr_ctl.sv:96:+ w0v[j] = wen0 & (waddr0[4:0] == 5'(j)); design/dec/el2_dec_gpr_ctl.sv:97:+ w1v[j] = wen1 & (waddr1[4:0] == 5'(j)); design/dec/el2_dec_gpr_ctl.sv:98:+ w2v[j] = wen2 & (waddr2[4:0] == 5'(j)); design/dec/el2_dec_gpr_ctl.sv:99:+ gpr_in[j] = ({32{w0v[j]}} & wd0[31:0]) |

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_veer.sv:26:-`include "el2_param.vh" design/el2_veer.sv:27:- ) design/el2_veer.sv:28:- ( design/el2_veer.sv:29:- input logic clk, design/el2_veer.sv:30:- input logic rst_l, design/el2_veer.sv:31:- input logic dbg_rst_l, design/el2_veer.sv:32:- input logic [31:1] rst_vec, design/el2_veer.sv:33:- input logic nmi_int, design/el2_veer.sv:34:- input logic [31:1] nmi_vec, design/el2_veer.sv:35:- output logic core_rst_l, // This is "rst_l | dbg_rst_l" design/el2_veer.sv:36:- design/el2_veer.sv:37:- output logic active_l2clk, design/el2_veer.sv:38:- output logic free_l2clk, design/el2_veer.sv:39:- design/el2_veer.sv:40:- output logic [31:0] trace_rv_i_insn_ip, design/el2_veer.sv:41:- output logic [31:0] trace_rv_i_address_ip, design/el2_veer.sv:42:- output logic trace_rv_i_valid_ip, design/el2_veer.sv:43:- output logic trace_rv_i_exception_ip, design/el2_veer.sv:44:- output logic [4:0] trace_rv_i_ecause_ip, design/el2_veer.sv:45:- output logic trace_rv_i_interrupt_ip, design/el2_veer.sv:46:- output logic [31:0] trace_rv_i_tval_ip, design/el2_veer.sv:47:- design/el2_veer.sv:48:- design/el2_veer.sv:49:- output logic dccm_clk_override, design/el2_veer.sv:50:- output logic icm_clk_override, design/el2_veer.sv:51:- output logic dec_tlu_core_ecc_disable, design/el2_veer.sv:52:- design/el2_veer.sv:53:- // external halt/run interface design/el2_veer.sv:54:- input logic i_cpu_halt_req, // Asynchronous Halt request to CPU design/el2_veer.sv:55:- input logic i_cpu_run_req, // Asynchronous Restart request to CPU design/el2_veer.sv:56:- output logic o_cpu_halt_ack, // Core Acknowledge to Halt request design/el2_veer.sv:57:- output logic o_cpu_halt_status, // 1'b1 indicates processor is halted design/el2_veer.sv:58:- output logic o_cpu_run_ack, // Core Acknowledge to run request design/el2_veer.sv:59:- output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request design/el2_veer.sv:60:- design/el2_veer.sv:61:- input logic [31:4] core_id, // CORE ID design/el2_veer.sv:62:- design/el2_veer.sv:63:- // external MPC halt/run interface design/el2_veer.sv:64:- input logic mpc_debug_halt_req, // Async halt request design/el2_veer.sv:65:- input logic mpc_debug_run_req, // Async run request design/el2_veer.sv:66:- input logic mpc_reset_run_req, // Run/halt after reset design/el2_veer.sv:67:- output logic mpc_debug_halt_ack, // Halt ack design/el2_veer.sv:68:- output logic mpc_debug_run_ack, // Run ack design/el2_veer.sv:69:- output logic debug_brkpt_status, // debug breakpoint design/el2_veer.sv:70:- design/el2_veer.sv:71:- output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc design/el2_veer.sv:72:- output logic dec_tlu_perfcnt1, design/el2_veer.sv:73:- output logic dec_tlu_perfcnt2, design/el2_veer.sv:74:- output logic dec_tlu_perfcnt3, design/el2_veer.sv:75:- design/el2_veer.sv:76:- // DCCM ports design/el2_veer.sv:77:- output logic dccm_wren, design/el2_veer.sv:78:- output logic dccm_rden, design/el2_veer.sv:79:- output logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo, design/el2_veer.sv:80:- output logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi, design/el2_veer.sv:81:- output logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo, design/el2_veer.sv:82:- output logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi, design/el2_veer.sv:83:- output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo, design/el2_veer.sv:84:- output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi, design/el2_veer.sv:85:- design/el2_veer.sv:86:- input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, design/el2_veer.sv

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_veer.sv:463:- input logic [pt.PIC_TOTAL_INT:1] extintsrc_req, design/el2_veer.sv:464:- input logic timer_int, design/el2_veer.sv:465:- input logic soft_int, design/el2_veer.sv:466:- input logic scan_mode design/el2_veer.sv:462:+ input logic [pt.PIC_TOTAL_INT:1] extintsrc_req, design/el2_veer.sv:463:+ input logic timer_int, design/el2_veer.sv:464:+ input logic soft_int, design/el2_veer.sv:465:+ input logic scan_mode

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_veer_wrapper.sv:607:- // Since all the signals in this block are tied to constant, we exclude this from coverage analysis design/el2_veer_wrapper.sv:608:- /*verilator coverage_off*/ design/el2_veer_wrapper.sv:609:- wire lsu_axi_awvalid; design/el2_veer_wrapper.sv:610:- wire lsu_axi_awready; design/el2_veer_wrapper.sv:611:- wire [pt.LSU_BUS_TAG-1:0] lsu_axi_awid; design/el2_veer_wrapper.sv:612:- wire [31:0] lsu_axi_awaddr; design/el2_veer_wrapper.sv:613:- wire [3:0] lsu_axi_awregion; design/el2_veer_wrapper.sv:614:- wire [7:0] lsu_axi_awlen; design/el2_veer_wrapper.sv:615:- wire [2:0] lsu_axi_awsize; design/el2_veer_wrapper.sv:616:- wire [1:0] lsu_axi_awburst; design/el2_veer_wrapper.sv:617:- wire lsu_axi_awlock; design/el2_veer_wrapper.sv:618:- wire [3:0] lsu_axi_awcache; design/el2_veer_wrapper.sv:619:- wire [2:0] lsu_axi_awprot; design/el2_veer_wrapper.sv:620:- wire [3:0] lsu_axi_awqos; design/el2_veer_wrapper.sv:621:- design/el2_veer_wrapper.sv:622:- design/el2_veer_wrapper.sv:623:- wire lsu_axi_wvalid; design/el2_veer_wrapper.sv:624:- wire lsu_axi_wready; design/el2_veer_wrapper.sv:625:- wire [63:0] lsu_axi_wdata; design/el2_veer_wrapper.sv:626:- wire [7:0] lsu_axi_wstrb; design/el2_veer_wrapper.sv:627:- wire lsu_axi_wlast; design/el2_veer_wrapper.sv:628:- design/el2_veer_wrapper.sv:629:- wire lsu_axi_bvalid; design/el2_veer_wrapper.sv:630:- wire lsu_axi_bready; design/el2_veer_wrapper.sv:631:- wire [1:0] lsu_axi_bresp; design/el2_veer_wrapper.sv:632:- wire [pt.LSU_BUS_TAG-1:0] lsu_axi_bid; design/el2_veer_wrapper.sv:633:- design/el2_veer_wrapper.sv:634:- // AXI Read Channels design/el2_veer_wrapper.sv:635:- wire lsu_axi_arvalid; design/el2_veer_wrapper.sv:636:- wire lsu_axi_arready; design/el2_veer_wrapper.sv:637:- wire [pt.LSU_BUS_TAG-1:0] lsu_axi_arid; design/el2_veer_wrapper.sv:638:- wire [31:0] lsu_axi_araddr; design/el2_veer_wrapper.sv:639:- wire [3:0] lsu_axi_arregion; design/el2_veer_wrapper.sv:640:- wire [7:0] lsu_axi_arlen; design/el2_veer_wrapper.sv:641:- wire [2:0] lsu_axi_arsize; design/el2_veer_wrapper.sv:642:- wire [1:0] lsu_axi_arburst; design/el2_veer_wrapper.sv:643:- wire lsu_axi_arlock; design/el2_veer_wrapper.sv:644:- wire [3:0] lsu_axi_arcache; design/el2_veer_wrapper.sv:645:- wire [2:0] lsu_axi_arprot; design/el2_veer_wrapper.sv:646:- wire [3:0] lsu_axi_arqos; design/el2_veer_wrapper.sv:647:- design/el2_veer_wrapper.sv:648:- wire lsu_axi_rvalid; design/el2_veer_wrapper.sv:649:- wire lsu_axi_rready; design/el2_veer_wrapper.sv:650:- wire [pt.LSU_BUS_TAG-1:0] lsu_axi_rid; design/el2_veer_wrapper.sv:651:- wire [63:0] lsu_axi_rdata; design/el2_veer_wrapper.sv:652:- wire [1:0] lsu_axi_rresp; design/el2_veer_wrapper.sv:653:- wire lsu_axi_rlast; design/el2_veer_wrapper.sv:654:- design/el2_veer_wrapper.sv:655:- assign lsu_axi_awready = '0; design/el2_veer_wrapper.sv:656:- assign lsu_axi_wready = '0; design/el2_veer_wrapper.sv:657:- assign lsu_axi_bvalid = '0; design/el2_veer_wrapper.sv:658:- assign lsu_axi_bresp = '0; d

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_veer_wrapper.sv:895:- .main_core_regfile(regfile.veer_rf_sink), design/el2_veer_wrapper.sv:896:-`endif // `ifdef RV_LOCKSTEP_REGFILE_ENABLE design/el2_veer_wrapper.sv:897:- .corruption_detected(lockstep_corruption_detected), design/el2_veer_wrapper.sv:898:- .* design/el2_veer_wrapper.sv:899:- ); design/el2_veer_wrapper.sv:900:-`endif // `ifdef RV_LOCKSTEP_ENABLE design/el2_veer_wrapper.sv:901:- design/el2_veer_wrapper.sv:902:- // Instantiate the mem design/el2_veer_wrapper.sv:903:- el2_mem #(.pt(pt)) mem ( design/el2_veer_wrapper.sv:904:- .clk(active_l2clk), design/el2_veer_wrapper.sv:905:- .rst_l(core_rst_l), design/el2_veer_wrapper.sv:906:- .mem_export(el2_mem_export), design/el2_veer_wrapper.sv:907:- .* design/el2_veer_wrapper.sv:908:- ); design/el2_veer_wrapper.sv:909:- design/el2_veer_wrapper.sv:910:- design/el2_veer_wrapper.sv:911:- logic unused_dmi_hard_reset; design/el2_veer_wrapper.sv:912:- // JTAG/DMI instance design/el2_veer_wrapper.sv:913:- dmi_wrapper dmi_wrapper ( design/el2_veer_wrapper.sv:914:- // JTAG signals design/el2_veer_wrapper.sv:915:- .trst_n (jtag_trst_n), // JTAG reset design/el2_veer_wrapper.sv:916:- .tck (jtag_tck), // JTAG clock design/el2_veer_wrapper.sv:917:- .tms (jtag_tms), // Test mode select design/el2_veer_wrapper.sv:918:- .tdi (jtag_tdi), // Test Data Input design/el2_veer_wrapper.sv:919:- .tdo (jtag_tdo), // Test Data Output design/el2_veer_wrapper.sv:920:- .tdoEnable (jtag_tdoEn), // Test Data Output enable design/el2_veer_wrapper.sv:921:- // Processor Signals design/el2_veer_wrapper.sv:922:- .core_rst_n (dbg_rst_l), // Debug reset, active low design/el2_veer_wrapper.sv:923:- .core_clk (clk), // Core clock design/el2_veer_wrapper.sv:924:- .jtag_id (jtag_id), // JTAG ID design/el2_veer_wrapper.sv:925:- .rd_data (dmi_rdata), // Read data from Processor design/el2_veer_wrapper.sv:926:- .reg_wr_data (dmi_wdata), // Write data to Processor design/el2_veer_wrapper.sv:927:- .reg_wr_addr (dmi_addr), // Write address to Processor design/el2_veer_wrapper.sv:928:- .reg_en (dmi_en), // Write interface bit to Processor design/el2_veer_wrapper.sv:929:- .reg_wr_en (dmi_wr_en), // Write enable to Processor design/el2_veer_wrapper.sv:930:- .dmi_hard_reset (unused_dmi_hard_reset) design/el2_veer_wrapper.sv:931:- ); design/el2_veer_wrapper.sv:932:- design/el2_veer_wrapper.sv:933:- // DMI core/uncore mux design/el2_veer_wrapper.sv:934:- dmi_mux dmi_mux ( design/el2_veer_wrapper.sv:935:- .uncore_enable (dmi_uncore_enable), design/el2_veer_wrapper.sv:936:- design/el2_veer_wrapper.sv:937:- .dmi_en (dmi_en), design/el2_veer_wrapper.sv:938:- .dmi_wr_en (dmi_wr_en), design/el2_veer_wrapper.sv:939:- .dmi_addr (dmi_addr), design/el2_veer_wrapper.sv:940:- .dmi_wdata (dmi_wdata), design/el2_veer_wrapper.sv:941:- .dmi_rdata (dmi_rdata), design/el2_veer_wrapper.sv:942:- design/el2_veer_wrapper.sv:943:- .dmi_core_en (dmi_reg_en), design/el2_veer_wrapper.sv:944:- .dmi_core_wr_en (dmi_reg_wr_en), design/el2_veer_wrapper.sv:945:- .dmi_core_addr (dmi_reg_addr), design/el2_veer_wrapper.sv:946:- .dmi_core_wdata (dmi_reg_wdata), design/el2_veer_wrapper.sv:947:- .dmi_core_rdata (dmi_reg_rdata), design/el2_veer_wrapper.sv:948:- design/el2_veer_wrapper.sv:949:- .dmi_uncore_en (dmi_uncore_en), design/el2_veer_wrapper.sv:950:- .dmi_uncore_wr_en (dmi_uncore_wr_en), design/el2_veer_wrapper.sv:951:- .dmi_uncore_addr (dmi_uncore_addr), design/el2_