Add initial DCLS support and documentation

.github/workflows/test-uarch.yml

@@ -58,6 +58,7 @@ jobs:
           - "block/pmp"
           - "block/dmi"
           - "block/lsu_tl"
+          - "block/dcls"
     env:
       CCACHE_DIR: "/opt/verification/.cache/"
       DEBIAN_FRONTEND: "noninteractive"

configs/veer.config

@@ -207,6 +207,12 @@ Parameters that can be set by the end user:
           number of PMP entries
      -set=smepmp = {0, 1}
           Enable Smepmp PMP extension
+     -set=lockstep_enable = {0, 1}
+          Enable Dual Core Lockstep (DCLS) in the core
+     -set=lockstep_regfile_enable = {0, 1}
+          Enable observing register file in the DCLS
+     -set=lockstep_delay = {2, 3, 4}
+          Set delay value for the Dual Core Lockstep
 
 
 Additionally the following may be set for bus masters and slaves using the -set=var=value option:
@@ -279,6 +285,9 @@ my $lsu2dma = 0;
 
 my $pmp_entries=16;
 my $smepmp=0;
+my $lockstep_enable=0;
+my $lockstep_regfile_enable=0;
+my $lockstep_delay=3;
 
 $user_mode=0;
 $ret_stack_size=8;
@@ -1056,6 +1065,9 @@ our %config = (#{{{
     "protection" => {                                                   # Design parms, Overridable - static MPU
         "pmp_entries"         => "$pmp_entries",
         "smepmp"              => "$smepmp",
+        "lockstep_enable"     => "$lockstep_enable",
+        "lockstep_regfile_enable" => "$lockstep_regfile_enable",
+        "lockstep_delay"      => "$lockstep_delay",
         "inst_access_enable0" => "0x0",
         "inst_access_addr0"   => "0x00000000",
         "inst_access_mask0"   => "0xffffffff",
@@ -1159,6 +1171,9 @@ our %verilog_parms = (
 
         "pmp_entries"         => '7',
         "smepmp"              => '1',
+        "lockstep_enable"     => '1',
+        "lockstep_regfile_enable" => '1',
+        "lockstep_delay"      => '3',
         "inst_access_enable0" => '1',
         "inst_access_addr0"   => '32',
         "inst_access_mask0"   => '32',
@@ -1386,6 +1401,7 @@ if ($config{core}{div_new}==0 && $config{core}{div_bit}!=1) {
 }
 
 $c=$config{protection}{pmp_entries};       if (!($c==64 || $c==16 || $c==0))                       { die("$helpusage\n\nFAIL: pmp_entries must be either 0, 16 or 64 !!!\n\n"); }
+$c=$config{protection}{lockstep_delay};    if ($config{protection}{lockstep_enable} && ($c<2 || $c>4)) { die("$helpusage\n\nFAIL: lockstep_delay must fit in range <2, 4> !!!\n\n"); }
 $c=$config{protection}{inst_access_addr0}; if ((hex($c)&0x3f) != 0)                                { die("$helpusage\n\nFAIL: inst_access_addr0 lower 6b must be 0s $c !!!\n\n"); }
 $c=$config{protection}{inst_access_addr1}; if ((hex($c)&0x3f) != 0)                                { die("$helpusage\n\nFAIL: inst_access_addr1 lower 6b must be 0s !!!\n\n"); }
 $c=$config{protection}{inst_access_addr2}; if ((hex($c)&0x3f) != 0)                                { die("$helpusage\n\nFAIL: inst_access_addr2 lower 6b must be 0s !!!\n\n"); }
@@ -1851,6 +1867,10 @@ our %widths = (
 );
 #}}}
 
+my $d=$config{protection}{lockstep_enable}; if ($d==0 || !grep(/lockstep_enable=1/, @sets))  { delete $config{"protection"}{"lockstep_enable"}; }
+$c=$config{protection}{lockstep_delay}; if ($d==0 || ($c==0 && !grep(/lockstep_delay=/, @sets))) { delete $config{"protection"}{"lockstep_delay"}; }
+$c=$config{protection}{lockstep_regfile_enable}; if ($d==0 || ($c==0 || !grep(/lockstep_regfile_enable=/, @sets))) { delete $config{"protection"}{"lockstep_regfile_enable"}; }
+
 print "\nVeeR configuration for target=$target\n\n";
 dump_define("","", \%config,[]);
 

design/dec/el2_dec.sv

@@ -319,6 +319,10 @@ module el2_dec
     output logic dec_tlu_dccm_clk_override,   // override DCCM clock domain gating
     output logic dec_tlu_icm_clk_override,    // override ICCM clock domain gating
 
+`ifdef RV_LOCKSTEP_REGFILE_ENABLE
+    el2_regfile_if.veer_rf_src regfile,
+`endif
+
     output logic dec_tlu_i0_commit_cmt,  // committed i0 instruction
     input  logic scan_mode               // Flop scan mode control
 
@@ -418,14 +422,52 @@ module el2_dec
 
   el2_dec_decode_ctl #(.pt(pt)) decode (.*);
 
+`ifdef RV_LOCKSTEP_REGFILE_ENABLE
+      el2_regfile_if regfile_if ();
+      assign regfile.gpr.ra = regfile_if.gpr.ra;
+      assign regfile.gpr.sp = regfile_if.gpr.sp;
+      assign regfile.gpr.fp = regfile_if.gpr.fp;
+      assign regfile.gpr.a0 = regfile_if.gpr.a0;
+      assign regfile.gpr.a1 = regfile_if.gpr.a1;
+      assign regfile.gpr.a2 = regfile_if.gpr.a2;
+      assign regfile.gpr.a3 = regfile_if.gpr.a3;
+      assign regfile.gpr.a4 = regfile_if.gpr.a4;
+      assign regfile.gpr.a5 = regfile_if.gpr.a5;
+      assign regfile.gpr.a6 = regfile_if.gpr.a6;
+      assign regfile.gpr.a7 = regfile_if.gpr.a7;
+
+      assign regfile.tlu.pc        = regfile_if.tlu.pc;
+      assign regfile.tlu.npc       = regfile_if.tlu.npc;
+      assign regfile.tlu.mstatus   = regfile_if.tlu.mstatus;
+      assign regfile.tlu.mie       = regfile_if.tlu.mie;
+      assign regfile.tlu.mtvec     = regfile_if.tlu.mtvec;
+      assign regfile.tlu.mscratch  = regfile_if.tlu.mscratch;
+      assign regfile.tlu.mepc      = regfile_if.tlu.mepc;
+      assign regfile.tlu.mcause    = regfile_if.tlu.mcause;
+      assign regfile.tlu.mtval     = regfile_if.tlu.mtval;
+      assign regfile.tlu.mip       = regfile_if.tlu.mip;
+      assign regfile.tlu.mcyclel   = regfile_if.tlu.mcyclel;
+      assign regfile.tlu.mcycleh   = regfile_if.tlu.mcycleh;
+      assign regfile.tlu.minstretl = regfile_if.tlu.minstretl;
+      assign regfile.tlu.minstreth = regfile_if.tlu.minstreth;
+      assign regfile.tlu.mrac      = regfile_if.tlu.mrac;
+`endif
 
-  el2_dec_tlu_ctl #(.pt(pt)) tlu (.*);
+  el2_dec_tlu_ctl #(.pt(pt)
+  ) tlu (
+`ifdef RV_LOCKSTEP_REGFILE_ENABLE
+      .regfile(regfile_if.veer_tlu_rf),
+`endif
+      .*);
 
 
   el2_dec_gpr_ctl #(
       .pt(pt)
   ) arf (
       .*,
+`ifdef RV_LOCKSTEP_REGFILE_ENABLE
+      .regfile(regfile_if.veer_gpr_rf),
+`endif
       // inputs
       .raddr0(dec_i0_rs1_d[4:0]),
       .raddr1(dec_i0_rs2_d[4:0]),

design/dec/el2_dec_gpr_ctl.sv

@@ -39,15 +39,33 @@
     output logic [31:0] rd0,         // read data
     output logic [31:0] rd1,
 
+`ifdef RV_LOCKSTEP_REGFILE_ENABLE
+    el2_regfile_if.veer_gpr_rf regfile,
+`endif
+
     input  logic        scan_mode
 );
 
    logic [31:1] [31:0] gpr_out;      // 31 x 32 bit GPRs
    logic [31:1] [31:0] gpr_in;
    logic [31:1] w0v,w1v,w2v;
    logic [31:1] gpr_wr_en;
 
+`ifdef RV_LOCKSTEP_REGFILE_ENABLE
+   assign regfile.gpr.ra = gpr_out[1][31:0]; // x1
+   assign regfile.gpr.sp = gpr_out[2][31:0]; // x2
+   assign regfile.gpr.fp = gpr_out[8][31:0]; // x8
+   assign regfile.gpr.a0 = gpr_out[10][31:0]; // x10
+   assign regfile.gpr.a1 = gpr_out[11][31:0]; // x11
+   assign regfile.gpr.a2 = gpr_out[12][31:0]; // x12
+   assign regfile.gpr.a3 = gpr_out[13][31:0]; // x13
+   assign regfile.gpr.a4 = gpr_out[14][31:0]; // x14
+   assign regfile.gpr.a5 = gpr_out[15][31:0]; // x15
+   assign regfile.gpr.a6 = gpr_out[16][31:0]; // x16
+   assign regfile.gpr.a7 = gpr_out[17][31:0]; // x17
+`endif
+
    // GPR Write Enables
    assign gpr_wr_en[31:1] = (w0v[31:1] | w1v[31:1] | w2v[31:1]);
    for ( genvar j=1; j<32; j++ )  begin : gpr
       rvdffe #(32) gprff (.*, .en(gpr_wr_en[j]), .din(gpr_in[j][31:0]), .dout(gpr_out[j][31:0]));

design/dec/el2_dec_tlu_ctl.sv

@@ -236,6 +236,10 @@ import el2_pkg::*;
    output logic  dec_tlu_dccm_clk_override, // override DCCM clock domain gating
    output logic  dec_tlu_icm_clk_override,  // override ICCM clock domain gating
 
+`ifdef RV_LOCKSTEP_REGFILE_ENABLE
+   el2_regfile_if.veer_tlu_rf regfile,
+`endif
+
 `ifdef RV_USER_MODE
 
    // Privilege mode
@@ -2627,6 +2631,25 @@ assign dec_csr_legal_d = ( dec_csr_any_unq_d &
                            ~(dec_csr_wen_unq_d & (csr_mvendorid | csr_marchid | csr_mimpid | csr_mhartid | csr_mdseac | csr_meihap)) // that's not a write to a RO CSR
                            );
    // CSR read mux
+logic [31:0] mstatus_rf, mie_rf, mtvec_rf, mscratch_rf, mepc_rf, mcause_rf, mtval_rf, mip_rf, mcyclel_rf, mcycleh_rf, minstretl_rf, minstreth_rf, mrac_rf;
+`ifdef RV_USER_MODE
+assign mstatus_rf = {14'b0, mstatus[MSTATUS_MPRV], 4'b0, ~mstatus[MSTATUS_MPP], ~mstatus[MSTATUS_MPP], 3'b0, mstatus[MSTATUS_MPIE], 3'b0, mstatus[MSTATUS_MIE], 3'b0};
+`else
+assign mstatus_rf = {19'b0, 2'b11, 3'b0, mstatus[MSTATUS_MPIE], 3'b0, mstatus[MSTATUS_MIE], 3'b0};
+`endif
+assign mie_rf = {1'b0, mie[5:3], 16'b0, mie[2], 3'b0, mie[1], 3'b0, mie[0], 3'b0};
+assign mtvec_rf = {mtvec[30:1], 1'b0, mtvec[0]};
+assign mscratch_rf = mscratch[31:0];
+assign mepc_rf = {mepc[31:1], 1'b0};
+assign mcause_rf = mcause[31:0];
+assign mtval_rf = mtval[31:0];
+assign mip_rf = {1'b0, mip[5:3], 16'b0, mip[2], 3'b0, mip[1], 3'b0, mip[0], 3'b0};
+assign mcyclel_rf = mcyclel[31:0];
+assign mcycleh_rf = mcycleh_inc[31:0];
+assign minstretl_rf = minstretl_read[31:0];
+assign minstreth_rf = minstreth_read[31:0];
+assign mrac_rf = mrac[31:0];
+
 assign dec_csr_rddata_d[31:0] = (
 `ifdef RV_USER_MODE
                                   ({32{csr_misa}}      & 32'h40101104) |
@@ -2637,24 +2660,20 @@ assign dec_csr_rddata_d[31:0] = (
                                   ({32{csr_marchid}}   & 32'h00000010) |
                                   ({32{csr_mimpid}}    & 32'h4) |
                                   ({32{csr_mhartid}}   & {core_id[31:4], 4'b0}) |
-`ifdef RV_USER_MODE
-                                  ({32{csr_mstatus}}   & {14'b0, mstatus[MSTATUS_MPRV], 4'b0, ~mstatus[MSTATUS_MPP], ~mstatus[MSTATUS_MPP], 3'b0, mstatus[MSTATUS_MPIE], 3'b0, mstatus[MSTATUS_MIE], 3'b0}) |
-`else
-                                  ({32{csr_mstatus}}   & {19'b0, 2'b11, 3'b0, mstatus[MSTATUS_MPIE], 3'b0, mstatus[MSTATUS_MIE], 3'b0}) |
-`endif
-                                  ({32{csr_mtvec}}     & {mtvec[30:1], 1'b0, mtvec[0]}) |
-                                  ({32{csr_mip}}       & {1'b0, mip[5:3], 16'b0, mip[2], 3'b0, mip[1], 3'b0, mip[0], 3'b0}) |
-                                  ({32{csr_mie}}       & {1'b0, mie[5:3], 16'b0, mie[2], 3'b0, mie[1], 3'b0, mie[0], 3'b0}) |
-                                  ({32{csr_mcyclel}}   & mcyclel[31:0]) |
-                                  ({32{csr_mcycleh}}   & mcycleh_inc[31:0]) |
-                                  ({32{csr_minstretl}} & minstretl_read[31:0]) |
-                                  ({32{csr_minstreth}} & minstreth_read[31:0]) |
-                                  ({32{csr_mscratch}}  & mscratch[31:0]) |
-                                  ({32{csr_mepc}}      & {mepc[31:1], 1'b0}) |
-                                  ({32{csr_mcause}}    & mcause[31:0]) |
+                                  ({32{csr_mstatus}}   & mstatus_rf[31:0]) |
+                                  ({32{csr_mtvec}}     & mtvec_rf) |
+                                  ({32{csr_mip}}       & mip_rf) |
+                                  ({32{csr_mie}}       & mie_rf) |
+                                  ({32{csr_mcyclel}}   & mcyclel_rf) |
+                                  ({32{csr_mcycleh}}   & mcycleh_rf) |
+                                  ({32{csr_minstretl}} & minstretl_rf) |
+                                  ({32{csr_minstreth}} & minstreth_rf) |
+                                  ({32{csr_mscratch}}  & mscratch_rf) |
+                                  ({32{csr_mepc}}      & mepc_rf) |
+                                  ({32{csr_mcause}}    & mcause_rf) |
                                   ({32{csr_mscause}}   & {28'b0, mscause[3:0]}) |
-                                  ({32{csr_mtval}}     & mtval[31:0]) |
-                                  ({32{csr_mrac}}      & mrac[31:0]) |
+                                  ({32{csr_mtval}}     & mtval_rf) |
+                                  ({32{csr_mrac}}      & mrac_rf) |
                                   ({32{csr_mdseac}}    & mdseac[31:0]) |
                                   ({32{csr_meivt}}     & {meivt[31:10], 10'b0}) |
                                   ({32{csr_meihap}}    & {meivt[31:10], meihap[9:2], 2'b0}) |
@@ -2714,7 +2733,24 @@ assign dec_csr_rddata_d[31:0] = (
                                   ({32{dec_pmp_read_d}} & dec_pmp_rddata_d[31:0])
                                   );
 
-
+`ifdef RV_LOCKSTEP_REGFILE_ENABLE
+   // Expose the register file
+   assign regfile.tlu.pc = pc_r;
+   assign regfile.tlu.npc = npc_r;
+   assign regfile.tlu.mstatus = mstatus_rf;
+   assign regfile.tlu.mie = mie_rf;
+   assign regfile.tlu.mtvec = mtvec_rf;
+   assign regfile.tlu.mscratch = mscratch_rf;
+   assign regfile.tlu.mepc = mepc_rf;
+   assign regfile.tlu.mcause = mcause_rf;
+   assign regfile.tlu.mtval = mtval_rf;
+   assign regfile.tlu.mip = mip_rf;
+   assign regfile.tlu.mcyclel = mcyclel_rf;
+   assign regfile.tlu.mcycleh = mcycleh_rf;
+   assign regfile.tlu.minstretl = minstretl_rf;
+   assign regfile.tlu.minstreth = minstreth_rf;
+   assign regfile.tlu.mrac = mrac_rf;
+`endif
 
 endmodule // el2_dec_tlu_ctl
 

design/el2_veer.sv

@@ -23,7 +23,7 @@
 module el2_veer
 import el2_pkg::*;
 #(
 `include "el2_param.vh"
  )
   (
    input logic                  clk,
@@ -455,7 +455,12 @@
    output logic                 dccm_ecc_single_error,
    output logic                 dccm_ecc_double_error,
 
+`ifdef RV_LOCKSTEP_REGFILE_ENABLE
+   // Register file
+   el2_regfile_if.veer_rf_src regfile,
+`endif
+
    input logic [pt.PIC_TOTAL_INT:1]           extintsrc_req,
    input logic                   timer_int,
    input logic                   soft_int,
    input logic                   scan_mode