Fix mixup and clearify ClockDomain details

source/SpinalHDL/Structuring/clock_domain.rst

@@ -55,7 +55,8 @@ This definition takes five parameters:
      - The goal of this signal is to disable the clock on the whole clock domain without having to manually implement that on each synchronous element
      - null
    * - ``frequency``
-     - Allows you to specify the frequency of the given clock domain and later read it in your design
+     - Allows you to specify the frequency of the given clock domain and later read it in your design.
+       This parameter does not generate and PLL or other hardware to control the frequency
      - UnknownFrequency
    * - ``config``
      - Specify the polarity of signals and the nature of the reset
@@ -246,6 +247,12 @@ Once created, you have to assign the ``ClockDomain``'s signals, as shown in the
      }
    }
 
+.. warning::
+   In other components then the one you created the ClockDomain in, you must not use ``.clock`` and ``.reset``,
+   but ``.readClockWire`` and ``.readResetWire`` as listed below. For the global ClockDomain you must always
+   use those ``.readXXX`` functions.
+
+
 External clock
 ^^^^^^^^^^^^^^
 
@@ -271,7 +278,7 @@ The arguments to the ``ClockDomain.external`` function are exactly the same as i
        val result = out UInt (4 bits)
      }
 
-     // On the top level you have two signals  :
+     // On the top level you have two signals  :
      //     myClockName_clk and myClockName_reset
      val myClockDomain = ClockDomain.external("myClockName")
 
@@ -344,10 +351,10 @@ The returned ``ClockDomain`` instance has the following functions that can be ca
      - Return a signal derived from the clock signal
      - Bool
    * - readResetWire
-     - Return a signal derived from the soft reset signal
+     - Return a signal derived from the reset signal
      - Bool
    * - readSoftResetWire
-     - Return a signal derived from the reset signal
+     - Return a signal derived from the soft reset signal
      - Bool
    * - readClockEnableWire
      - Return a signal derived from the clock enable signal
@@ -362,7 +369,6 @@ The returned ``ClockDomain`` instance has the following functions that can be ca
      - Return True when the clock enable is active
      - Bool
 
-
 An example is included below where a UART controller uses the frequency specification to set its clock divider:
 
 .. code-block:: scala