Merge pull request #241 from yportne13/master

add description for SpinalEnum resetValue in RegIf field
SpinalHDL · Feb 4, 2024 · 1424d20 · 1424d20
2 parents 346066c + dfd9df2
commit 1424d20
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Showing 3 changed files with 205 additions and 172 deletions.
diff --git a/source/SpinalHDL/Libraries/regIf.rst b/source/SpinalHDL/Libraries/regIf.rst
@@ -17,9 +17,9 @@ Automatic address allocation
 
   class RegBankExample extends Component {
     val io = new Bundle {
-      apb = Apb3(Apb3Config(16,32))
+      apb = slave(Apb3(Apb3Config(16,32)))
     }
-    val busif = Apb3BusInterface(io.apb,(0x0000, 100 Byte)
+    val busif = Apb3BusInterface(io.apb,(0x0000, 100 Byte))
     val M_REG0  = busif.newReg(doc="REG0")
     val M_REG1  = busif.newReg(doc="REG1")
     val M_REG2  = busif.newReg(doc="REG2")
@@ -269,6 +269,19 @@ example2: interrupt raw reg with foce interface for software
    val raw    = RAW.field(Bool(), AccessType.W1C,    resetValue = 0, doc = s"raw, default 0" )
                 FORCE.parasiteField(raw, AccessType.W1S,   resetValue = 0, doc = s"force, write 1 set, debug use" )
 
+**CASE6:** ``SpinalEnum``
+
+When the field type is SpinalEnum, the resetValue specifies the index of the enum elements.
+
+.. code:: scala
+
+   object UartCtrlTxState extends SpinalEnum(defaultEncoding = binaryOneHot) {
+      val sIdle, sStart, sData, sParity, sStop = newElement()
+   }
+
+   val raw = M_REG2.field(UartCtrlTxState(), AccessType.RW, resetValue = 2, doc="state")
+   // raw will be init to sData
+
 Byte Mask
 =========
 

diff --git a/source/locale/gettext/SpinalHDL/Libraries/regIf.pot b/source/locale/gettext/SpinalHDL/Libraries/regIf.pot
@@ -8,7 +8,7 @@ msgid ""
 msgstr ""
 "Project-Id-Version: SpinalHDL \n"
 "Report-Msgid-Bugs-To: \n"
-"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"POT-Creation-Date: 2024-02-04 07:37+0000\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <[email protected]>\n"
@@ -62,15 +62,15 @@ msgid "Most of these come from UVM specification"
 msgstr ""
 
 #: ../../SpinalHDL/Libraries/regIf.rst:75
-#: ../../SpinalHDL/Libraries/regIf.rst:397
-#: ../../SpinalHDL/Libraries/regIf.rst:418
+#: ../../SpinalHDL/Libraries/regIf.rst:410
+#: ../../SpinalHDL/Libraries/regIf.rst:431
 msgid "AccessType"
 msgstr ""
 
 #: ../../SpinalHDL/Libraries/regIf.rst:75
-#: ../../SpinalHDL/Libraries/regIf.rst:397
-#: ../../SpinalHDL/Libraries/regIf.rst:418
-#: ../../SpinalHDL/Libraries/regIf.rst:436
+#: ../../SpinalHDL/Libraries/regIf.rst:410
+#: ../../SpinalHDL/Libraries/regIf.rst:431
+#: ../../SpinalHDL/Libraries/regIf.rst:449
 msgid "Description"
 msgstr ""
 
@@ -79,8 +79,8 @@ msgid "From"
 msgstr ""
 
 #: ../../SpinalHDL/Libraries/regIf.rst:77
-#: ../../SpinalHDL/Libraries/regIf.rst:402
-#: ../../SpinalHDL/Libraries/regIf.rst:421
+#: ../../SpinalHDL/Libraries/regIf.rst:415
+#: ../../SpinalHDL/Libraries/regIf.rst:434
 msgid "RO"
 msgstr ""
 
@@ -117,9 +117,9 @@ msgid "UVM"
 msgstr ""
 
 #: ../../SpinalHDL/Libraries/regIf.rst:78
-#: ../../SpinalHDL/Libraries/regIf.rst:400
-#: ../../SpinalHDL/Libraries/regIf.rst:401
-#: ../../SpinalHDL/Libraries/regIf.rst:420
+#: ../../SpinalHDL/Libraries/regIf.rst:413
+#: ../../SpinalHDL/Libraries/regIf.rst:414
+#: ../../SpinalHDL/Libraries/regIf.rst:433
 msgid "RW"
 msgstr ""
 
@@ -192,7 +192,7 @@ msgid "w: clears all bits, r: sets all bits"
 msgstr ""
 
 #: ../../SpinalHDL/Libraries/regIf.rst:87
-#: ../../SpinalHDL/Libraries/regIf.rst:399
+#: ../../SpinalHDL/Libraries/regIf.rst:412
 msgid "W1C"
 msgstr ""
 
@@ -515,173 +515,181 @@ msgstr ""
 msgid "example2: interrupt raw reg with foce interface for software"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:273
+#: ../../SpinalHDL/Libraries/regIf.rst:272
+msgid "**CASE6:** ``SpinalEnum``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:274
+msgid "When the field type is SpinalEnum, the resetValue specifies the index of the enum elements."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/regIf.rst:286
 msgid "Byte Mask"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:275
+#: ../../SpinalHDL/Libraries/regIf.rst:288
 msgid "withStrb"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:279
+#: ../../SpinalHDL/Libraries/regIf.rst:292
 msgid "Typical Example"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:281
+#: ../../SpinalHDL/Libraries/regIf.rst:294
 msgid "Batch create REG-Address and fields register"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:321
+#: ../../SpinalHDL/Libraries/regIf.rst:334
 msgid "Interrupt Factory"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:323
+#: ../../SpinalHDL/Libraries/regIf.rst:336
 msgid "Manual writing interruption"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:366
+#: ../../SpinalHDL/Libraries/regIf.rst:379
 msgid "this is a very tedious and repetitive work, a better way is to use the \"factory\" paradigm to auto-generate the documentation for each signal."
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:368
+#: ../../SpinalHDL/Libraries/regIf.rst:381
 msgid "now the InterruptFactory can do that."
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:370
+#: ../../SpinalHDL/Libraries/regIf.rst:383
 msgid "Easy Way create interruption:"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:394
+#: ../../SpinalHDL/Libraries/regIf.rst:407
 msgid "IP level interrupt Factory"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:397
-#: ../../SpinalHDL/Libraries/regIf.rst:418
+#: ../../SpinalHDL/Libraries/regIf.rst:410
+#: ../../SpinalHDL/Libraries/regIf.rst:431
 msgid "Register"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:399
+#: ../../SpinalHDL/Libraries/regIf.rst:412
 msgid "RAW"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:399
+#: ../../SpinalHDL/Libraries/regIf.rst:412
 msgid "int raw register, set by int event, clear when bus write 1"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:400
+#: ../../SpinalHDL/Libraries/regIf.rst:413
 msgid "FORCE"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:400
+#: ../../SpinalHDL/Libraries/regIf.rst:413
 msgid "int force register, for SW debug use"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:401
-#: ../../SpinalHDL/Libraries/regIf.rst:420
+#: ../../SpinalHDL/Libraries/regIf.rst:414
+#: ../../SpinalHDL/Libraries/regIf.rst:433
 msgid "MASK"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:401
-#: ../../SpinalHDL/Libraries/regIf.rst:420
+#: ../../SpinalHDL/Libraries/regIf.rst:414
+#: ../../SpinalHDL/Libraries/regIf.rst:433
 msgid "int mask register, 1: off; 0: open; defualt 1 int off"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:402
-#: ../../SpinalHDL/Libraries/regIf.rst:421
+#: ../../SpinalHDL/Libraries/regIf.rst:415
+#: ../../SpinalHDL/Libraries/regIf.rst:434
 msgid "STATUS"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:402
+#: ../../SpinalHDL/Libraries/regIf.rst:415
 msgid "int status, Read Only, ``status = raw && ! mask``"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:408
-#: ../../SpinalHDL/Libraries/regIf.rst:426
+#: ../../SpinalHDL/Libraries/regIf.rst:421
+#: ../../SpinalHDL/Libraries/regIf.rst:439
 msgid "SpinalUsage:"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:415
+#: ../../SpinalHDL/Libraries/regIf.rst:428
 msgid "SYS level interrupt merge"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:421
+#: ../../SpinalHDL/Libraries/regIf.rst:434
 msgid "int status, RO, ``status = int_level && ! mask``"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:433
+#: ../../SpinalHDL/Libraries/regIf.rst:446
 msgid "Spinal Factory"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:436
+#: ../../SpinalHDL/Libraries/regIf.rst:449
 msgid "BusInterface method"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:438
-#: ../../SpinalHDL/Libraries/regIf.rst:440
+#: ../../SpinalHDL/Libraries/regIf.rst:451
+#: ../../SpinalHDL/Libraries/regIf.rst:453
 msgid "``InterruptFactory(regNamePre: String, triggers: Bool*)``"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:438
+#: ../../SpinalHDL/Libraries/regIf.rst:451
 msgid "create RAW/FORCE/MASK/STATUS for pulse event"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:439
+#: ../../SpinalHDL/Libraries/regIf.rst:452
 msgid "``InterruptFactoryNoForce(regNamePre: String, triggers: Bool*)``"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:439
+#: ../../SpinalHDL/Libraries/regIf.rst:452
 msgid "create RAW/MASK/STATUS for pulse event"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:440
+#: ../../SpinalHDL/Libraries/regIf.rst:453
 msgid "create MASK/STATUS for level_int merge"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:441
-#: ../../SpinalHDL/Libraries/regIf.rst:443
+#: ../../SpinalHDL/Libraries/regIf.rst:454
+#: ../../SpinalHDL/Libraries/regIf.rst:456
 msgid "``InterruptFactoryAt(addrOffset: Int, regNamePre: String, triggers: Bool*)``"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:441
+#: ../../SpinalHDL/Libraries/regIf.rst:454
 msgid "create RAW/FORCE/MASK/STATUS for pulse event at addrOffset"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:442
+#: ../../SpinalHDL/Libraries/regIf.rst:455
 msgid "``InterruptFactoryNoForceAt(addrOffset: Int, regNamePre: String, triggers: Bool*)``"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:442
+#: ../../SpinalHDL/Libraries/regIf.rst:455
 msgid "create RAW/MASK/STATUS for pulse event at addrOffset"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:443
+#: ../../SpinalHDL/Libraries/regIf.rst:456
 msgid "create MASK/STATUS for level_int merge at addrOffset"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:447
+#: ../../SpinalHDL/Libraries/regIf.rst:460
 msgid "Example"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:479
+#: ../../SpinalHDL/Libraries/regIf.rst:492
 msgid "DefaultReadValue"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:481
+#: ../../SpinalHDL/Libraries/regIf.rst:494
 msgid "When the software reads a reserved address, the current policy is to return normally, readerror=0. In order to facilitate software debugging, the read back value can be configured, which is 0 by default"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:499
+#: ../../SpinalHDL/Libraries/regIf.rst:512
 msgid "Developers Area"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:501
+#: ../../SpinalHDL/Libraries/regIf.rst:514
 msgid "You can add your document Type by extending the `BusIfVistor` Trait"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:503
+#: ../../SpinalHDL/Libraries/regIf.rst:516
 msgid "``case class Latex(fileName : String) extends BusIfVisitor{ ... }``"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/regIf.rst:505
+#: ../../SpinalHDL/Libraries/regIf.rst:518
 msgid "BusIfVistor give access BusIf.RegInsts to do what you want"
 msgstr ""