update .pot files

source/locale/gettext/SpinalHDL/Simulation/bootstraps.pot

@@ -8,7 +8,7 @@ msgid ""
 msgstr ""
 "Project-Id-Version: SpinalHDL \n"
 "Report-Msgid-Bugs-To: \n"
-"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"POT-Creation-Date: 2024-02-01 10:15+0000\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <[email protected]>\n"
@@ -168,70 +168,90 @@ msgstr ""
 msgid "Note is it equivalent to:"
 msgstr ""
 
+#: ../../SpinalHDL/Simulation/bootstraps.rst:159
+msgid "The location where the simulation files will be placed is defined by default in $WORKSPACE/$COMPILED."
+msgstr ""
+
 #: ../../SpinalHDL/Simulation/bootstraps.rst:161
-msgid "Note that by default, the simulation files will be placed into the ``simWorkspace/xxx`` folders. You can override the simWorkspace location by setting the ``SPINALSIM_WORKSPACE`` environment variable."
+msgid "$WORKSPACE being by default ``simWorkspace``, you can override it with the ``SPINALSIM_WORKSPACE`` environnement variable."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:162
+msgid "$COMPILED being the name of the toplevel being simulated."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:163
+msgid "The location of the wave file depend the backend used. For verilator it will be in the folder (``$WORKSPACE/$COMPILED/$TEST`` by default)."
 msgstr ""
 
 #: ../../SpinalHDL/Simulation/bootstraps.rst:164
+msgid "For the verilator backend, you can override the location of the test folder via the ``SimConfig.setTestPath(path)`` function."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:165
+msgid "You can retrieve the location of the test path durring simulation by calling the currentTestPath() function."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/bootstraps.rst:169
 msgid "Running multiple tests on the same hardware"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/bootstraps.rst:179
+#: ../../SpinalHDL/Simulation/bootstraps.rst:184
 msgid "Throw Success or Failure of the simulation from a thread"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/bootstraps.rst:181
+#: ../../SpinalHDL/Simulation/bootstraps.rst:186
 msgid "At any moment during a simulation you can call ``simSuccess`` or ``simFailure`` to end it."
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/bootstraps.rst:183
+#: ../../SpinalHDL/Simulation/bootstraps.rst:188
 msgid "It is possible to make a simulation fail when it is too long, for instance because the test-bench is waiting for a condition which never occurs. To do so, call ``SimTimeout(maxDuration)`` where ``maxDuration`` is the time (in simulation units of time) after the which the simulation should be considered to have failed."
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/bootstraps.rst:185
+#: ../../SpinalHDL/Simulation/bootstraps.rst:190
 msgid "For instance, to make the simulation fail after 1000 times the duration of a clock cycle:"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/bootstraps.rst:194
+#: ../../SpinalHDL/Simulation/bootstraps.rst:199
 msgid "Capturing wave for a given window before failure"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/bootstraps.rst:196
+#: ../../SpinalHDL/Simulation/bootstraps.rst:201
 msgid "In the case you have a very long simulation, and you don't want to capture the wave on all of it (too bug, too slow), you have mostly 2 ways to do it."
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/bootstraps.rst:198
+#: ../../SpinalHDL/Simulation/bootstraps.rst:203
 msgid "Either you know already at which ``simTime`` the simulation failed, in which case you can do the following in your testbench :"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/bootstraps.rst:205
+#: ../../SpinalHDL/Simulation/bootstraps.rst:210
 msgid "Or you can run a dual lock-step simulation, with one running a bit delayed from the the other one, and which will start recording the wave once the leading simulation had a failure."
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/bootstraps.rst:207
+#: ../../SpinalHDL/Simulation/bootstraps.rst:212
 msgid "To do this, you can use the DualSimTracer utility, with parameters for the compiled hardware, the window of time you want to capture before failure, and a seed."
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/bootstraps.rst:209
+#: ../../SpinalHDL/Simulation/bootstraps.rst:214
 msgid "Here is an example :"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/bootstraps.rst:214
+#: ../../SpinalHDL/Simulation/bootstraps.rst:219
 msgid "This will generate the following file structure :"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/bootstraps.rst:216
+#: ../../SpinalHDL/Simulation/bootstraps.rst:221
 msgid "simWorkspace/Toplevel/explorer/stdout.log : stdout of the simulation which is ahead"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/bootstraps.rst:217
+#: ../../SpinalHDL/Simulation/bootstraps.rst:222
 msgid "simWorkspace/Toplevel/tracer/stdout.log : stdout of the simulation doing the wave tracing"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/bootstraps.rst:218
+#: ../../SpinalHDL/Simulation/bootstraps.rst:223
 msgid "simWorkspace/Toplevel/tracer.fst : Waveform of the failure"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/bootstraps.rst:220
+#: ../../SpinalHDL/Simulation/bootstraps.rst:225
 msgid "The scala terminal will show the explorer simulation stdout."
 msgstr ""

source/locale/gettext/SpinalHDL/Simulation/index.pot

@@ -8,7 +8,7 @@ msgid ""
 msgstr ""
 "Project-Id-Version: SpinalHDL \n"
 "Report-Msgid-Bugs-To: \n"
-"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"POT-Creation-Date: 2024-02-01 10:15+0000\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <[email protected]>\n"
@@ -33,11 +33,11 @@ msgid "`Verilator <https://www.veripool.org/verilator/>`_"
 msgstr ""
 
 #: ../../SpinalHDL/Simulation/index.rst:14
-msgid "`GHDL <http://ghdl.free.fr/>`_ **(experimental, since SpinalHDL 1.4.1)**"
+msgid "`GHDL <http://ghdl.free.fr/>`_"
 msgstr ""
 
 #: ../../SpinalHDL/Simulation/index.rst:15
-msgid "`Icarus Verilog <https://steveicarus.github.io/iverilog/>`_ **(experimental, since SpinalHDL 1.4.1)**"
+msgid "`Icarus Verilog <https://steveicarus.github.io/iverilog/>`_"
 msgstr ""
 
 #: ../../SpinalHDL/Simulation/index.rst:16