fix(simtop): assert trace enable

src/test/scala/top/SimTop.scala

@@ -66,7 +66,7 @@ class SimTop(implicit p: Parameters) extends Module {
   soc.io.cacheable_check := DontCare
   soc.io.riscv_rst_vec.foreach(_ := 0x10000000L.U)
   l_soc.nmi.foreach(_.foreach(intr => { intr := false.B; dontTouch(intr) }))
-  soc.io.traceCoreInterface.foreach(_.fromEncoder.enable := false.B)
+  soc.io.traceCoreInterface.foreach(_.fromEncoder.enable := true.B)
   soc.io.traceCoreInterface.foreach(_.fromEncoder.stall  := false.B)
 
   // soc.io.rtc_clock is a div100 of soc.io.clock