fix(trace): remove traceTrap & tracePriv from trace pipeline

src/main/scala/xiangshan/backend/Backend.scala

@@ -247,6 +247,7 @@ class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parame
   ctrlBlock.io.fromTop.hartId := io.fromTop.hartId
   ctrlBlock.io.frontend <> io.frontend
   ctrlBlock.io.fromCSR.toDecode := intExuBlock.io.csrToDecode.get
+  ctrlBlock.io.fromCSR.traceCSR := intExuBlock.io.csrio.get.traceCSR
   ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback
   ctrlBlock.io.fromMem.stIn <> io.mem.stIn
   ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation
@@ -256,8 +257,6 @@ class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parame
   ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt
   ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget
   ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet
-  ctrlBlock.io.robio.csr.traceTrapInfo := intExuBlock.io.csrio.get.traceTrapInfo
-  ctrlBlock.io.robio.csr.tracePriv := intExuBlock.io.csrio.get.tracePriv
   ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event
   ctrlBlock.io.robio.csr.criticalErrorState := intExuBlock.io.csrio.get.criticalErrorState
   ctrlBlock.io.robio.lsq <> io.mem.robLsqIO

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -270,9 +270,14 @@ class CtrlBlockImp(
     trace.io.fromPcMem(i) := pcMem.io.rdata(pcMemIdx).getPc(RegEnable(trace.toPcMem(i).bits.ftqOffset.get, traceValid))
   }
 
-  io.traceCoreInterface.toEncoder.cause     := trace.io.toEncoder.trap.cause.asUInt
-  io.traceCoreInterface.toEncoder.tval      := trace.io.toEncoder.trap.tval.asUInt
-  io.traceCoreInterface.toEncoder.priv      := trace.io.toEncoder.priv.asUInt
+  // Trap/Xret only occor in block(0).
+  val tracePriv = Mux(Itype.isTrapOrXret(trace.io.toEncoder.blocks(0).bits.tracePipe.itype),
+    io.fromCSR.traceCSR.lastPriv,
+    io.fromCSR.traceCSR.currentPriv
+  )
+  io.traceCoreInterface.toEncoder.cause     := io.fromCSR.traceCSR.cause.asUInt
+  io.traceCoreInterface.toEncoder.tval      := io.fromCSR.traceCSR.tval.asUInt
+  io.traceCoreInterface.toEncoder.priv      := tracePriv
   io.traceCoreInterface.toEncoder.iaddr     := VecInit(trace.io.toEncoder.blocks.map(_.bits.iaddr.get)).asUInt
   io.traceCoreInterface.toEncoder.itype     := VecInit(trace.io.toEncoder.blocks.map(_.bits.tracePipe.itype)).asUInt
   io.traceCoreInterface.toEncoder.iretire   := VecInit(trace.io.toEncoder.blocks.map(_.bits.tracePipe.iretire)).asUInt
@@ -730,6 +735,7 @@ class CtrlBlockIO()(implicit p: Parameters, params: BackendParams) extends XSBun
   val frontend = Flipped(new FrontendToCtrlIO())
   val fromCSR = new Bundle{
     val toDecode = Input(new CSRToDecode)
+    val traceCSR = Input(new TraceCSR)
   }
   val toIssueBlock = new Bundle {
     val flush = ValidIO(new Redirect)

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -100,8 +100,8 @@ class CSRFileIO(implicit p: Parameters) extends XSBundle {
   val trapTarget = Output(new TargetPCBundle)
   val interrupt = Output(Bool())
   val wfi_event = Output(Bool())
-  val traceTrapInfo = ValidIO(new TraceTrap)
-  val tracePriv = Output(new TracePriv)
+  //trace
+  val traceCSR = Output(new TraceCSR)
   // from LSQ
   val memExceptionVAddr = Input(UInt(XLEN.W))
   val memExceptionGPAddr = Input(UInt(XLEN.W))

src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala

@@ -190,8 +190,7 @@ class NewCSR(implicit val p: Parameters) extends Module
       // Instruction fetch address translation type
       val instrAddrTransType = new AddrTransType
       // trace
-      val traceTrapInfo = ValidIO(new TraceTrap)
-      val tracePriv = Output(new TracePriv)
+      val traceCSR = Output(new TraceCSR)
       // custom
       val custom = new CSRCustomState
       val criticalErrorState = Bool()
@@ -1121,14 +1120,13 @@ class NewCSR(implicit val p: Parameters) extends Module
   val currentPriv = privForTrace
   val lastPriv = RegEnable(privForTrace, Priv.M, (xret || io.fromRob.trap.valid))
 
-  io.status.tracePriv.lastPriv       := lastPriv
-  io.status.tracePriv.currentPriv    := privForTrace
-  io.status.traceTrapInfo.valid      := RegNext(io.fromRob.trap.valid)
-  io.status.traceTrapInfo.bits.cause := Mux1H(
+  io.status.traceCSR.lastPriv       := lastPriv
+  io.status.traceCSR.currentPriv    := privForTrace
+  io.status.traceCSR.cause := Mux1H(
     Seq(privState.isModeM, privState.isModeHS, privState.isModeVS),
     Seq(mcause.rdata,      scause.rdata,       vscause.rdata)
   )
-  io.status.traceTrapInfo.bits.tval  := Mux1H(
+  io.status.traceCSR.tval  := Mux1H(
     Seq(privState.isModeM, privState.isModeHS, privState.isModeVS),
     Seq(mtval.rdata,       stval.rdata,        vstval.rdata)
   )

src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala

@@ -309,8 +309,7 @@ class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg)
 
   csrOut.debugMode := csrMod.io.status.debugMode
 
-  csrOut.traceTrapInfo := csrMod.io.status.traceTrapInfo
-  csrOut.tracePriv     := csrMod.io.status.tracePriv
+  csrOut.traceCSR := csrMod.io.status.traceCSR
 
   csrOut.customCtrl match {
     case custom =>

src/main/scala/xiangshan/backend/rob/Rob.scala

@@ -1231,12 +1231,8 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP
   /**
    * trace
    */
-  val traceTrapInfoFromCsr = io.csr.traceTrapInfo
-  val tracePrivInfoFromCsr = io.csr.tracePriv
 
   // trace output
-  val traceTrap = io.trace.traceCommitInfo.trap
-  val tracePriv = io.trace.traceCommitInfo.priv
   val traceValids = io.trace.traceCommitInfo.blocks.map(_.valid)
   val traceBlocks = io.trace.traceCommitInfo.blocks
   val traceBlockInPipe = io.trace.traceCommitInfo.blocks.map(_.bits.tracePipe)
@@ -1255,27 +1251,13 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP
     traceValids(i) := iretire =/= 0.U
   }
 
-  val t_idle :: t_waiting :: Nil = Enum(2)
-  val traceState = RegInit(t_idle)
-  when(traceState === t_idle){
-    when(io.exception.valid){
-      traceState := t_waiting
-    }
-  }.elsewhen(traceState === t_waiting){
-    when(traceTrapInfoFromCsr.valid){
-      traceState := t_idle
-      traceBlocks(0).bits.tracePipe.itype := Mux(io.exception.bits.isInterrupt,
-        Itype.Interrupt,
-        Itype.Exception
-      )
-      traceValids(0) := true.B
-    }
+  when(RegNext(io.exception.valid)){
+    traceBlocks(0).bits.tracePipe.itype := Mux(io.exception.bits.isInterrupt,
+      Itype.Interrupt,
+      Itype.Exception
+    )
+    traceValids(0) := true.B
   }
-  traceTrap := traceTrapInfoFromCsr.bits
-  tracePriv := Mux(traceValids(0) && Itype.isTrapOrXret(traceBlocks(0).bits.tracePipe.itype),
-    tracePrivInfoFromCsr.lastPriv,
-    tracePrivInfoFromCsr.currentPriv
-  )
 
   /**
    * debug info

src/main/scala/xiangshan/backend/rob/RobBundles.scala

@@ -217,8 +217,6 @@ class RobCSRIO(implicit p: Parameters) extends XSBundle {
   val isXRet     = Input(Bool())
   val wfiEvent   = Input(Bool())
   val criticalErrorState = Input(Bool())
-  val traceTrapInfo = Flipped(ValidIO(new TraceTrap))
-  val tracePriv = Input(new TracePriv)
 
   val fflags     = Output(Valid(UInt(5.W)))
   val vxsat      = Output(Valid(Bool()))

src/main/scala/xiangshan/backend/trace/Interface.scala

@@ -7,12 +7,9 @@ import utils.NamedUInt
 import xiangshan.HasXSParameter
 import xiangshan.frontend.{BrType, FtqPtr, PreDecodeInfo}
 
-class TraceTrap(implicit val p: Parameters) extends Bundle with HasXSParameter {
+class TraceCSR(implicit val p: Parameters) extends Bundle with HasXSParameter {
   val cause = UInt(CauseWidth.W)
   val tval  = UInt(TvalWidth.W)
-}
-
-class TracePriv extends Bundle  {
   val lastPriv    = Priv()
   val currentPriv = Priv()
 }
@@ -31,8 +28,6 @@ class TraceBlock(hasIaddr: Boolean, iretireWidth: Int)(implicit val p: Parameter
 }
 
 class TraceBundle(hasIaddr: Boolean, blockSize: Int, iretireWidth: Int)(implicit val p: Parameters) extends Bundle with HasXSParameter {
-  val priv = Priv()
-  val trap = Output(new TraceTrap)
   val blocks = Vec(blockSize, ValidIO(new TraceBlock(hasIaddr, iretireWidth)))
 }
 

src/main/scala/xiangshan/backend/trace/Trace.scala

@@ -41,12 +41,6 @@ class Trace(implicit val p: Parameters) extends Module with HasXSParameter {
   val s1_out = WireInit(0.U.asTypeOf(s1_in))
 
   for(i <- 0 until CommitWidth) {
-    // Trap/Xret only occor in block(0).
-    if(i == 0) {
-      s1_out.priv := RegEnable(s1_in.priv, s1_in.blocks(0).valid)
-      s1_out.trap.cause := RegEnable(s1_in.trap.cause, 0.U, s1_in.blocks(0).valid && Itype.isTrap(s1_in.blocks(0).bits.tracePipe.itype))
-      s1_out.trap.tval := RegEnable(s1_in.trap.tval, 0.U, s1_in.blocks(0).valid && Itype.isTrap(s1_in.blocks(0).bits.tracePipe.itype))
-    }
     s1_out.blocks(i).valid := RegEnable(s1_in.blocks(i).valid, false.B, !blockCommit)
     s1_out.blocks(i).bits := RegEnable(s1_in.blocks(i).bits, 0.U.asTypeOf(s1_in.blocks(i).bits), s1_in.blocks(i).valid)
   }
@@ -70,8 +64,6 @@ class Trace(implicit val p: Parameters) extends Module with HasXSParameter {
   toPcMem := s3_in_groups.blocks
 
   for(i <- 0 until TraceGroupNum) {
-    toEncoder.priv := s3_out_groups.priv
-    toEncoder.trap := s3_out_groups.trap
     toEncoder.blocks(i).valid := s3_out_groups.blocks(i).valid
     toEncoder.blocks(i).bits.iaddr.foreach(_ := Mux(s3_out_groups.blocks(i).valid, fromPcMem(i), 0.U))
     toEncoder.blocks(i).bits.tracePipe := s3_out_groups.blocks(i).bits.tracePipe

src/main/scala/xiangshan/backend/trace/TraceBuffer.scala

@@ -23,11 +23,7 @@ class TraceBuffer(implicit val p: Parameters) extends Module
   })
 
   // buffer: compress info from robCommit
-  val traceTrap    = Reg(new TraceTrap)
-  val tracePriv    = Reg(Priv())
   val traceEntries = Reg(Vec(CommitWidth, ValidIO(new TraceBlock(false, IretireWidthCompressed))))
-  traceTrap := io.in.fromRob.trap
-  tracePriv := io.in.fromRob.priv
 
   val blockCommit = RegInit(false.B) // to rob
 
@@ -82,8 +78,6 @@ class TraceBuffer(implicit val p: Parameters) extends Module
    * deq from traceEntries
    */
   val blockOut = WireInit(0.U.asTypeOf(io.out.groups))
-  blockOut.priv := tracePriv
-  blockOut.trap := traceTrap
   for(i <- 0 until TraceGroupNum) {
     when(deqPtrPre + i.U < enqPtr) {
       blockOut.blocks(i) := traceEntries((deqPtrPre + i.U).value)