-
Notifications
You must be signed in to change notification settings - Fork 46
Release Notes
This release contains:
-
Reference projects
- all reference projects and reference cores have been migrated to Vivado 2020.1, Ubuntu 2020.4 LTS and Python 3,
- new standard core: nic_output_queues - this core is based on the output queue ip core and enables a backpressure to the output port lookup,
- fix in 10g attachment unit core in TX queue: this enables more efficient version of TX queue and allows to handle deficit idle count (fix from P4-NetFPGA project),
- reference_nic project has a backpressure enabled in the output queues.
-
Contrib Projects
- corundum: ports of verilog-pcie, verilog-ehternet, and corundum projects to NetFPGA SUME board.
-
Driver
- new SUME riffa driver for FreeBSD.
For known issues please visit this wiki page.
The open issues can also be seen on this link.
The procedure to open new issue tickets can be viewed here.
This release contains:
-
Bug Fix
- nf_axis_converter_v1_0_0: Fix timing issue on the path between the nf_axis_converter and the tx_queue. The timing issue was causing the nf_axis_converter output to be incorrect, which in turn caused the MAC to reject packets of certain lengths. Added an AXIS pipeline stage on the output of the nf_axis_converter.
-
Contrib Projects
- lake: Layered Key-value store, a hardware-based implementation of memcached server
- reference_emu_dns: Implementation of a DNS server with the Emu framework and integrated into the SUME reference data path
- nic_v2: Reference NIC with the new DMA engine core
-
Contrib Cores
- db_v1_0_1: A key-value cache which stores key-value pair on DRAM and BRAM
- div_v1_0_0: A packet distributer, based on UDP port number and this module acts as in-network computing on-demand controller
- emudns_output_port_lookup_v1_0_0: Output port lookup core generated by the Emu framework with DNS functionality
- input_arbiter_6in_v1_0_0: Provides support for an additional internal high-priority 50Gbps queue
- nf_naudit_dma_v1_0_0: New DMA engine
- nf_sume_pktgen_v1_0_0: Enables internal packet injection at full speed (~50Gbps)
For known issues please visit this wiki page.
The open issues can also be seen on this link.
The procedure to open new issue tickets can be viewed here.
This release contains:
-
Fix for manual test via uart not working
- Using UART to run manual test did not work previously for reference_switch and reference_switch_lite. This has been fixed. See https://github.com/NetFPGA/NetFPGA-SUME-live/issues/37
-
Fix for acceptance test crash in headless mode
- NfSumeTest.py is run during acceptance test. This script assumed the presence of a display which caused a crash. The fix now allows the script to be run without a display.
-
New contribution - script to generate the regs_gen.py file
- The new file csv_gen.py can be used instead of running the excel macro inside module_generation.xlsm
For known issues please visit this wiki page.
The open issues can also be seen on this link.
The procedure to open new issue tickets can be viewed here.
This release contains:
- Hot fix
(Cores)
- nf_10ge_interface_v1_0_0 : Disabled deficit idle count on TX MAC in 10G ports as enabling it causes packet drop under some scenarios.
For known issues please visit this wiki page.
The open issues can also be seen on this link.
The procedure to open new issue tickets can be viewed here.
This release contains:
-
Update
- Ubuntu 16.04 -- Operating System Setup Guide (wiki-page) has been updated
-
Cores
- nf_10ge_interface_v1_0_0 : Enabled deficit idle count on TX MAC in 10G ports
- barrier_v1_0_0 : move the inactivity timeout inside barrier definition
-
Contrib Projects
- reference_switch_lcam : increase CAM size 982 to 1024 entries
For known issues please visit this wiki page.
The open issues can also be seen on this link.
The procedure to open new issue tickets can be viewed here.
This release contains:
- Hotfixes
- Fix the OPL of the reference_router to handle the backpresure and tuser of the modified OQs
- Fixed tuser in reference_switch output port lookup
- Fix output queues handling of tuser + changed AXI-S bus to behave as in other modules
For known issues please visit this wiki page.
The open issues can also be seen on this link.
The procedure to open new issue tickets can be viewed here.
This release contains:
-
Update
- Xilinx Core
- cam_v1_1_0 : Change CAM type to BRAM to improve timing
- Projects
- reference_nic : Migrate to Vivado v2016.4
- reference_switch : Migrate to Vivado v2016.4
- reference_switch_lite : Migrate to Vivado v2016.4
- reference_router : Migrate to Vivado v2016.4
- acceptance_test : Migrate to Vivado v2016.4
- Xilinx Core
-
Bug Fix
- switch_output_port_lookup_v1_0_1 : Fix tuser signal handling
- output_queues_v1_0_0 : Fix output queues handling of tuser
- cam_v1_1_0 : Fix ternary mode
-
Contrib Projects
- encap_decap : encap/decap VLAN tag
- reference_switch_lcam : reference_switch with large CAM
-
Contrib Cores
- vlan_adder_v1_0_0 : used in encap_decap contrib-project
- vlan_remover_v1_0_0 : used in encap_decap contrib-project
- nic_output_port_lookup_v4_0_0 : used in encap_decap contrib-project
- lcam_output_port_lookup_v1_0_0 : used in reference_switch_lcam contrib-project
-
Limitation
All the reference projects work, without any issue, in hosts with 64GB of memory, with Vivado v2016.4.
For known issues please visit this wiki page.
The open issues can also be seen on this link.
The procedure to open new issue tickets can be viewed here.
This release contains:
-
Updates
- nf_10ge_attachment_v1_0_0 : Fix the state machine conditions in tx and rx queue modules to revolve the interface stall issues. Fix the reset signal connection in tx and rx queue modules
-
Bug Fix
- reference_switch_lite : Fix the reset signal which caused negative slack in the reference_switch_lite bitfile
- axitools.py : Fix a typo, an undefined variable was crashing the script
For known issues please visit this wiki page.
The open issues can also be seen on this link.
The procedure to open new issue tickets can be viewed here.
This release contains:
-
Contributed Projects
-
Contributed Cores
- nfmac_10ge_interface_shared_v1_0_0 : Open-source version of the Xilinx ten_gig_eth_mac
- nfmac_10ge_interface_v1_0_0 : Open-source version of the Xilinx ten_gig_eth_mac
- delay_v1_0_0 : FIFO-based module that control latency based on timestamps -- wiki
- rate_limiter_v1_0_0 : FIFO-based module for pacing of data out of the FIFO -- wiki
- emu_output_port_lookup_v1_0_0 : Output Port Lookup module that supports the reference_emu project
-
For known issues please visit this wiki page.
The open issues can also be seen on this link.
The procedure to open new issue tickets can be viewed here.
This release contains:
-
Projects
- Reference router
-
Contributed projects
- BlueSwitch
-
Cores
- router_output_port_lookup_v1_0_0 : Implmentation of IPv4 Reference Router -- wiki page
-
Contributed cores
-
Tools
- Registers generation infrastructure: Updated version 2, support of indirect register access -- wiki page
-
Patch
- switch_output_port_lookup_v1_0_1 :
- Fix a typo in cam instantiation
- Update the implementation run, to more aggressive timing closure mode
- Add new CAM parameters (ADDR_TYPE, MATCH_ADDR_WIDTH)
- xparam2regdefines.py : Fix bug which produced multiple hashes
- switch_output_port_lookup_v1_0_1 :
-
Xilinx cores
- cam_v1_1_0/tcam_v1_1_0 : Add new CAM parameters in the wrappers to support the ADDR_TYPE and MATCH_ADDR_WIDTH
-
For known issues please visit this wiki page.
The open issues can also be seen on this link.
The procedure to open new issue tickets can be viewed here.
This release contains:
- Projects
- Acceptance Test: Added PCIe ibert test
- Patch
- NfSumeTest.py: Added a checkbox in the GUI of the acceptance_test to narrow down USB device listing
- Bug Fix
- Fixing a typo error in the Makefile of the acceptance_test project
- For known issues please visit this wiki page.
The open issues can also be seen on this link.
The procedure to open new issue tickets can be viewed here.
This release contains:
- Projects
- reference_switch ( uses a CAM based output port lookup) -- wiki page
- reference_switch_lite ( uses register based output port lookup) -- wiki page
(Note : The reference_switch_lite was the reference_switch project in release 1.0.0 )
- Cores
- cam_v1_0_0 : a CAM core based on Xilinx's xapp1151 core -- wiki page
- tcam_v1_0_0 : a TCAM core based on Xilinx's xapp1151 core -- wiki page
- switch_output_port_lookup_v1_0_0: learning switch output port lookup, with CAM based lookup table, with registers
- Bug Fix
- Fixing a typo error in multiple cores, where "+ +" appears instead of "+" in various counters.
- For known issues please visit this wiki page.
The open issues can also be seen on this link.
The procedure to open new issue tickets can be viewed here.
This release contains:
-
Projects
- Acceptance Test
- Reference NIC
- Reference Switch
-
Cores
- axi_sim_transactor_v1_0_0: drives an AXI Stream slave using stimuli from an AXI grammar formatted text file
- axis_sim_pkg_v1_0_0: stream simulation I/O support package
- axis_sim_record_v1_0_0: records traffic received from an AXI Stream master to an AXI grammar formatted text file
- axis_sim_stim_v1_0_0: drives an AXI Stream slave using stimuli from an AXI grammar formatted text file
- barrier_gluelogic_v1_0_0/ barrier_v1_0_0: aggregates barrier good notifications from individual modules and pushes out a global barrier good notification when all modules are ready
- fallthrough_small_fifo_v1_0_0: small fifo with fallthrough i.e. data valid when rd is high
- identifier_v1_0_0: used to identify the bitfile loaded in the FPGA (the time it was created and github version)
- input_arbiter_v1_0_0: input arbiter with registers
- nf_10ge_attachment_v1_0_0: clock and data conversion between 10GE port and NetFPGA data path
- nf_10ge_interface_shared_v1_0_0: 10GE SFP+ interface, contains the shared logic per quad of ports
- nf_10ge_interface_v1_0_0: 10GE SFP+ interface, without shared logic
- nf_axis_converter_v1_0_0: convert AXI4-Streams to different data width
- nf_riffa_dma_v1_0_0: NetFPGA-SUME adapted RIFFA DMA Engine
- nic_output_port_lookup_v1_0_0: nic output port lookup with registers
- output_queues_v1_0_0: BRAM output queues with registers
- switch_lite_output_port_lookup_v1_0_0: learning switch output port lookup, with registers-based lookup table, with registers
-
DMA
- RIFFA DMA Engine Operates over PCIe gen.2 x8
- SUME-RIFFA DMA driver v1.0.0
- rwaxi: application for registers access using SUME-RIFFA DMA driver
- generate_register_read: application for testing a project's registers read access using rwaxi
- generate_register_write: application for testing a project's registers write access using rwaxi
-
Tools
- Registers generation infrastructure
- NFTest: Simulation and hardware test harness
- pci_rescan_run: PCI bus rescan script, following FPGA reconfiguration
- load_bitfile: FPGA configuration script
- interface_reconfig: generate configuration files for hardware tests
- settings: local machine path and project settings
-
Documentation
-
Contributed documents:
- SUME VC709 FMC: FMC pinout of NetFPGA SUME vs. Xilinx VC709
-
Contributed cores:
- nf_sume_sfp_clk_init: Clock init for the SUME SFP clock (SI5324)
-
For known issues please visit the following link:
https://github.com/NetFPGA/NetFPGA-SUME-public/wiki/Known-issues
To avoid any issues, we recommend cloning the repo to a new folder.