Releases: BU-Tools/uHAL_AXI_regmap
Releases · BU-Tools/uHAL_AXI_regmap
v3.0.0
v2.0 release
Release v2.0 (#8) * Add a wishbone compatible template * add new parser * refactored the code to be based on the new node structure * added a simple readme * restyle tree.py * changed dict has key * StringIO support for both python 2 and 3 * restyle node.py * fixed bitshift ambiguity * renamed Node to parserNode * include constructor for parserNode * code to build packages with parserNode * StringIO support for both python 2 and 3 * bug fixes * commenting out in progress code * renamed the files * fixed existing bug in vhdl generation. minor compatability fixes * Added axi register packages * Started organizing templates * Added initial work on template * untested version of bram addition * building version * fixes for more complicated xml * updates to checkout on another machine * Updates * working in ghdl sim * Added .git ignore * updates * modified state machine * Fixed invalid address * Working BRAM interface * Working BRAM interface * Added data valid to ram reads * Updated axireg repo for d64 packages * fixed stupid bug * Merged in changes * Adding wishbone template to repo * fixed missing d64 package * Updates to have standalone example * create script for unit test * create script for generate vhdl api * update code * add changes for building tree and error detection * include uhal import check and support for python 3 * fix typo * removed todos * changes to dict has_key * combined readme * Delete README.MD * to make parserNode works * include functions same as uhal * TEMP change outFileName dir * add print_function for python2 * changed node variable name in constructor to avoid confusion * fix outFileName dir * fix outFileName dir * remove empty lin * fix outFileName dir * removed with statement for python2 compatibility * move code for uhal and custom parser together * renamed build_vhdl_packages * created the parserTree class * renamed file * add unit test code for comparing uhal and custom parser * changes to import * changes to import * combine uhal parser and custom parser to one file * cleaned up the code * create files for testing parser * include code for deleting temp dir * fix regMapTemplate argument * imported subprocess * Refactor files and used argparser * Fixed fwinfo bug * Fixed dir removal bug. Changed templates to be have file with the same _map module in them * Adjusted some paths and arguments to interface better with SM/CM prebuild script * changed size default value * Fixed bug in uHAL building * Fix relative imports for python3 When using an __init__.py in python3 you must prefix the module name with a dot to indicate that the import is local within the package rather than coming from the pythonpath somewhere * Cleanup readme * Fix test packages script * Supply a default value of pkgTemplate to make it optional * Fix broken tester code Previously it would run on the address table XML file and generate PKG and MAP for every possible thing (each register would get its own empty map file...) Now generate a top level wrapper and use that instead * Use distutils string to bool instead of homebrew * Cleanup temp xml file after use * Commit tester outputs, can use git diff to check * Check git diff for changes in the test * Work toward PEP8 * Switch from dict to OrderedDict Otherwise order is not deterministic and produces different results between python2 and python3 (and probably under other conditions) so the unit test to check the VHDL outputs is not functional * Cleanup whitespace printing for BRAM * Cleaning without functional change * Add yaml to hdl output * Remove a * import * Whitespace * Also test on CM_USP * Fix non-deterministic behavior The time in only precision of seconds :( was used to create a "unique" file name.. multiple calls to the same function within the same second would generate the same "unique" file name and cause some conflict by parsing the wrong file Now users the actual tempfile module which creates guaranteed unique file names. The unit test now works regardless of the alignment of the stars * Whitespace + comments * Barf if an unknown parser is requested * Fix yml2hdl package default * Clean up decoder generation code No change in output, just cleaning the source * Whitespace + cleaned up format strings Trying to clean up a few things for my own readability, no functional change in the test outputs * Remove unused code * Add a makefile for the tester code * Make sure to clear the yml file before appending to it * Add wishbone output to the unit tester * Update wishbone template for pulsed signals * Accomodate both yml v1 and v2 headers * Clean wishbone folders in tester makefile * Fix yaml outputs * Add template field for additionalLibraries Needed for yml2hdl where defaults come from a separate package * Remove shared lib from yml2hdl defaults package Co-authored-by: Andrew Peck <[email protected]> Co-authored-by: DavidLi1355 <[email protected]> Co-authored-by: David <[email protected]> Co-authored-by: Andrew Peck <[email protected]>