release 1.0 (#18)

* release 1.0
- F6 -microcode timestamp
- HDMI on/off
- BC-correlator for ora orc configurable
- tcm board v0 renamed to tcm_proto
- Link ID changed to 0x20

firmware/FT0/PM/hdl/fit.vhd

@@ -294,7 +294,7 @@ signal ev_tout_cnt : STD_LOGIC_VECTOR (7 downto 0);
 signal CH_N0, CH_N1, CH_N0_0, CH_N1_0, CH_NUM : STD_LOGIC_VECTOR (3 downto 0);
 signal CH_NUM1, CH_NUM2 : STD_LOGIC_VECTOR (2 downto 0);
 signal WRDS_NUM : STD_LOGIC_VECTOR (2 downto 0);
-signal Orbit_ID, hspid_w32, hspid_r32, tstamp, hspib_32 : STD_LOGIC_VECTOR (31 downto 0);
+signal Orbit_ID, hspid_w32, hspid_r32, tstamp, hspib_32, mcu_tstamp : STD_LOGIC_VECTOR (31 downto 0);
 signal xadc_r, xadc_out : STD_LOGIC_VECTOR (15 downto 0);
 signal xadc_a: STD_LOGIC_VECTOR (6 downto 0);
 signal EV_ID_in, EV_ID_out : STD_LOGIC_VECTOR (55 downto 0);
@@ -408,26 +408,6 @@ component TDCCHAN is
 
    end component;
 
---   component GBT_TX_RX is
---       Port ( RESET : in  STD_LOGIC;
---              MgtRefClk : in  STD_LOGIC;
---              MGT_RX_P : in  STD_LOGIC;
---              MGT_RX_N : in  STD_LOGIC;
---              MGT_TX_P : out  STD_LOGIC;
---              MGT_TX_N : out  STD_LOGIC;
---              TXDataClk : in  STD_LOGIC;
---              TXData : in  STD_LOGIC_VECTOR (79 downto 0);
---              TXData_SC : in  STD_LOGIC_VECTOR (3 downto 0);
---              IsTXData : in  STD_LOGIC;
---              RXDataClk : out  STD_LOGIC;
---              RXData : out  STD_LOGIC_VECTOR (79 downto 0);
---              RXData_SC : out  STD_LOGIC_VECTOR (3 downto 0);
---              IsRXData : out  STD_LOGIC;
---              RX_ready : out  STD_LOGIC;
---              RX_errors : out  STD_LOGIC
---              );
---   end component;
-
       component EVENTID_FIFO
        Port ( clk : IN STD_LOGIC; 
        srst : IN STD_LOGIC;
@@ -1398,8 +1378,12 @@ if (HSCKI'event and HSCKI='0') then
             when 16#D8# to 16#e7#  => if (hspi_h='0') then HSPI_DATA<=ipbus_control_reg(to_integer(unsigned(hspi_addr(7 downto 0)))-16#D8#)(31 downto 16);
                                           else HSPI_DATA<=ipbus_control_reg(to_integer(unsigned(hspi_addr(7 downto 0)))-16#D8#)(15 downto 0); end if;
 
-            when 16#E8# to 16#FB# => HSPI_DATA<=hspib_32(31 downto 16); hspi_32l <=hspib_32(15 downto 0); 
+            when 16#E8# to 16#F6# => HSPI_DATA<=hspib_32(31 downto 16); hspi_32l <=hspib_32(15 downto 0);
+
+            when 16#F7#  => HSPI_DATA<=mcu_tstamp(31 downto 16); hspi_32l <=mcu_tstamp(15 downto 0); 
 
+            when 16#F8# to 16#FB# => HSPI_DATA<=hspib_32(31 downto 16); hspi_32l <=hspib_32(15 downto 0); 
+
             when 16#FC# to 16#FE# => HSPI_DATA<=(others=>'0'); hspi_32l <=xadc_r;
 
             when 16#FF#  => HSPI_DATA<=tstamp(31 downto 16); hspi_32l <=tstamp(15 downto 0);
@@ -1439,7 +1423,10 @@ if (SCKi'event and SCKi='0') then MISOI<=SPI_DATA(15); end if;
 if (SCKI'event and SCKI='1') then
 
         if (spi_bit_count="11111") then spi_bit_count<="10000"; spi_na<='1';
-          if  (spi_rd='0') then   spi_wr_data<=SPI_DATA(14 downto 0) & MOSII;  
+          if  (spi_rd='0') then  
+            if (spi_addr(7 downto 0) = x"F5") then mcu_tstamp(15 downto 0) <= SPI_DATA(14 downto 0) & MOSII; end if;
+            if (spi_addr(7 downto 0) = x"F6") then mcu_tstamp(31 downto 16) <= SPI_DATA(14 downto 0) & MOSII;  end if;
+            spi_wr_data<=SPI_DATA(14 downto 0) & MOSII;  
             if (spi_addr(7)='0') then  spi_wr_rdy<='1'; else if (spi_addr(6)='0') then spibuf_wr<='1'; end if; end if;
           end if;
          else 

firmware/FT0/TCM/hdl/BC_correlator.vhd

@@ -0,0 +1,102 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 01/05/2021 08:02:13 PM
+-- Design Name: 
+-- Module Name: BC_correlator - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity BC_correlator is
+    Port ( clk320  : in STD_LOGIC;
+           BC_cou : in STD_LOGIC_VECTOR (11 downto 0);
+           mt_cou : in STD_LOGIC_VECTOR (2 downto 0);
+           inc : in STD_LOGIC; 
+           clr : in STD_LOGIC;
+           ipb_clk : in STD_LOGIC;
+           rd : in STD_LOGIC;
+           addr : in STD_LOGIC_VECTOR (11 downto 0);
+           data : out STD_LOGIC_VECTOR (31 downto 0)
+           );
+end BC_correlator;
+
+architecture RTL of BC_correlator is
+
+signal ack0, clr_mem, clr_req, inc_i : STD_LOGIC;
+signal wea : STD_LOGIC_vector (0 downto 0);
+signal m_rd, m_wr : STD_LOGIC_vector (31 downto 0);
+
+COMPONENT BC_corr_mem
+  PORT (
+    clka : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+    dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+  );
+END COMPONENT;
+
+
+begin
+
+m0 : BC_corr_mem PORT MAP (clka => clk320, wea => wea, addra => BC_cou, dina => m_wr, douta => m_rd, clkb => ipb_clk, web => "0", addrb => addr, dinb => (others=>'0'), doutb => data);
+
+
+m_wr<= x"0000000" & "000" & inc_i when (clr_mem='1') else m_rd+1;
+
+process(clk320)
+begin
+if (clk320'event and clk320='1') then
+
+ if (clr='1') then clr_req<='1'; else 
+  if (clr_req='1') and (BC_cou=0) and (mt_cou="010") then clr_req<='0'; end if; 
+ end if;
+
+if  (BC_cou=0) and (mt_cou="010") then clr_mem<=clr_req; end if;
+
+if (mt_cou="011") then
+
+  inc_i<= inc;
+
+  if (clr_mem='1') or (inc='1') then wea(0)<= '1'; end if;
+
+else  
+ wea(0)<= '0';
+end if;
+
+
+
+end if;
+end process;
+
+end RTL;

firmware/FT0/TCM/hdl/pm-spi.vhd

@@ -47,7 +47,8 @@ entity pm_spi is
         spi_mosi : out STD_LOGIC;
         spi_miso : in STD_LOGIC;
         cnt_rd : in STD_LOGIC;
-        PM_rst : in STD_LOGIC
+        PM_rst : in STD_LOGIC;
+        ena  : in STD_LOGIC
         );
 
 end pm_spi;
@@ -60,7 +61,7 @@ signal A_old, A_spi : STD_LOGIC_VECTOR (7 downto 0);
 signal fifo_out : STD_LOGIC_VECTOR (31 downto 0);
 signal A_cou : STD_LOGIC_VECTOR (4 downto 0);
 signal cont, mode16, eoc, n_addr, rd_cou, smode, rd_spi, cs_spi, fifo_wr, fifo_rd, fifo_full, fifo_empty, reg_rd, spi_inp, rd_old : STD_LOGIC;
-signal xmg_sel, xmg_md, xmg_smpl, x_wait, cmd_rst, cmd_rst1, rst_rq : STD_LOGIC;
+signal xmg_sel, xmg_md, xmg_smpl, x_wait, cmd_rst, cmd_rst1, rst_rq, spi_sel_i : STD_LOGIC;
 signal fifo_cou : STD_LOGIC_VECTOR (9 downto 0);
 
 
@@ -99,14 +100,15 @@ xmg_sel<='1' when  (cs='1') and (A='1' & x"02") else '0';
 
 xmg_md<= (xmg_sel and not smode) or cmd_rst;
 
-spi_mosi<=Dreg(47);
+spi_mosi<=Dreg(47) and ena;
+spi_sel<= spi_sel_i and ena;
 
 spi_inp<=xmg_smpl when (xmg_md='1') else not spi_miso;
 
 A_spi<=A(7 downto 0) when (smode='0') else "110" & A_cou;
 rd_spi<= rd when (smode='0') else '1';
 
-spi_clk <= count(1) when ((count(7 downto 2)/="000000") and (xmg_md='0')) or  (x_wait='0') else '0';
+spi_clk <= count(1) when (((count(7 downto 2)/="000000") and (xmg_md='0')) or  (x_wait='0')) and (ena='1') else '0';
 
 
 mode16<= '1'  when A_spi(7 downto 4)<x"C" else '0';
@@ -147,7 +149,7 @@ if (rst='1') then rd_cou<='0'; smode<='0'; cmd_rst<='0'; rst_rq<='0';
  end if;  
 end if;
 
- if (rst='1') or ((cs_spi='0') and (smode='0') and (cmd_rst='0')) then count<=x"00"; spi_sel<='1';  Dreg(47)<='0'; cont<='0';
+ if (rst='1') or ((cs_spi='0') and (smode='0') and (cmd_rst='0')) then count<=x"00"; spi_sel_i<='1';  Dreg(47)<='0'; cont<='0';
   else
 
   if (count(1 downto 0)="11")  then xmg_smpl<= not spi_miso; end if;
@@ -158,9 +160,9 @@ end if;
     else  count<=count+1; end if;
  end if;
 
- if ((count=x"00") and (xmg_md='1')) or ((count=x"01") and (xmg_md='0') and (n_addr='0')) then spi_sel<='0';
+ if ((count=x"00") and (xmg_md='1')) or ((count=x"01") and (xmg_md='0') and (n_addr='0')) then spi_sel_i<='0';
    else 
-     if (count=x"05") and (xmg_md='0')  then  spi_sel<='1'; end if;
+     if (count=x"05") and (xmg_md='0')  then  spi_sel_i<='1'; end if;
  end if; 
 
 if ((count=x"01") and (n_addr='1')) or ((count=x"05") and (xmg_md='0')) then A_old<=A_spi; rd_old<=rd_spi; end if;