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Merge pull request #17 from dfinogee/master
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- ipbus updated, now all types of SFP connectors works
- project generated from tcl cleaned up; vertex time tune reg expanded
- projects cleaned up and some bug fixed
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@dfinogee
dfinogee authored Jan 20, 2021
2 parents f694ef7 + 96881fb commit 0543510
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Showing 22 changed files with 178 additions and 100 deletions.
2 changes: 1 addition & 1 deletion firmware/FT0/FTM_PM/ipcore_properties/gig_ethernet_pcs_pma_0.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,7 @@ CONFIG.SGMII_PHY_Mode string false false
CONFIG.S_AXI.INSERT_VIP string false 0
CONFIG.S_AXI_ACLK.INSERT_VIP string false 0
CONFIG.S_AXI_RESETN.INSERT_VIP string false 0
CONFIG.Standard string false 1000BASEX
CONFIG.Standard string false BOTH
CONFIG.SupportLevel string false Include_Shared_Logic_in_Example_Design
CONFIG.TXOUTCLK_PORT.INSERT_VIP string false 0
CONFIG.Timer_Format string false Time_of_day
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2 changes: 1 addition & 1 deletion firmware/FT0/FTM_PM/ipcore_properties/tri_mode_ethernet_mac_0.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ CONFIG.GTX_CLK_OUT.INSERT_VIP string false 0
CONFIG.Half_Duplex string false false
CONFIG.Int_Clk_Src string false user_clk2
CONFIG.Int_Mode_Type string false BASEX
CONFIG.MAC_Speed string false 1000_Mbps
CONFIG.MAC_Speed string false Tri_speed
CONFIG.MDIO_BOARD_INTERFACE string false Custom
CONFIG.MII_IO string false true
CONFIG.M_AXIS_RX.INSERT_VIP string false 0
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30 changes: 28 additions & 2 deletions firmware/FT0/FTM_PM/xdc/FIT_GBT_kc705_io.xdc
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Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,9 @@ set_property PACKAGE_PIN B25 [get_ports FMC_HPC_clk_A_n]

set_property PACKAGE_PIN H24 [get_ports LAS_EN]
set_property IOSTANDARD LVCMOS25 [get_ports LAS_EN]
set_property IOSTANDARD LVCMOS25 [get_ports SCOPE]
set_property PACKAGE_PIN E28 [get_ports SCOPE]


#set_property PACKAGE_PIN AG27 [get_ports TCM_TT0_P]
#set_property PACKAGE_PIN AJ26 [get_ports TCM_TA1_P]
Expand Down Expand Up @@ -146,8 +149,8 @@ set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_3]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_2]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_4]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_6]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_7]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_BUTTON_SW_C]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_7]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_BUTTON_SW_C]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_5]
#set_property IOSTANDARD LVCMOS25 [get_ports GPIO_SMA_J13]
#set_property IOSTANDARD LVCMOS25 [get_ports GPIO_SMA_J14]
Expand Down Expand Up @@ -246,3 +249,26 @@ set_property CFGBVS VCCO [current_design]
set_property PACKAGE_PIN Y29 [get_ports GPIO_DIP_SW0]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_DIP_SW0]


set_property OFFCHIP_TERM NONE [get_ports GPIO_SMA_J13]
set_property OFFCHIP_TERM NONE [get_ports TCM_SPI_MOSI]
set_property OFFCHIP_TERM NONE [get_ports TCM_SPI_SCK]
set_property OFFCHIP_TERM NONE [get_ports TCM_SPI_SEL]
set_property OFFCHIP_TERM NONE [get_ports LA[15]]
set_property OFFCHIP_TERM NONE [get_ports LA[14]]
set_property OFFCHIP_TERM NONE [get_ports LA[13]]
set_property OFFCHIP_TERM NONE [get_ports LA[12]]
set_property OFFCHIP_TERM NONE [get_ports LA[11]]
set_property OFFCHIP_TERM NONE [get_ports LA[10]]
set_property OFFCHIP_TERM NONE [get_ports LA[9]]
set_property OFFCHIP_TERM NONE [get_ports LA[8]]
set_property OFFCHIP_TERM NONE [get_ports LA[7]]
set_property OFFCHIP_TERM NONE [get_ports LA[6]]
set_property OFFCHIP_TERM NONE [get_ports LA[5]]
set_property OFFCHIP_TERM NONE [get_ports LA[4]]
set_property OFFCHIP_TERM NONE [get_ports LA[3]]
set_property OFFCHIP_TERM NONE [get_ports LA[2]]
set_property OFFCHIP_TERM NONE [get_ports LA[1]]
set_property OFFCHIP_TERM NONE [get_ports LA[0]]
set_property OFFCHIP_TERM NONE [get_ports sfp_rate_sel[1]]
set_property OFFCHIP_TERM NONE [get_ports sfp_rate_sel[0]]
2 changes: 1 addition & 1 deletion firmware/FT0/FTM_TCM/ipcore_properties/gig_ethernet_pcs_pma_0.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,7 @@ CONFIG.SGMII_PHY_Mode string false false
CONFIG.S_AXI.INSERT_VIP string false 0
CONFIG.S_AXI_ACLK.INSERT_VIP string false 0
CONFIG.S_AXI_RESETN.INSERT_VIP string false 0
CONFIG.Standard string false 1000BASEX
CONFIG.Standard string false BOTH
CONFIG.SupportLevel string false Include_Shared_Logic_in_Example_Design
CONFIG.TXOUTCLK_PORT.INSERT_VIP string false 0
CONFIG.Timer_Format string false Time_of_day
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2 changes: 1 addition & 1 deletion firmware/FT0/FTM_TCM/ipcore_properties/tri_mode_ethernet_mac_0.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ CONFIG.GTX_CLK_OUT.INSERT_VIP string false 0
CONFIG.Half_Duplex string false false
CONFIG.Int_Clk_Src string false user_clk2
CONFIG.Int_Mode_Type string false BASEX
CONFIG.MAC_Speed string false 1000_Mbps
CONFIG.MAC_Speed string false Tri_speed
CONFIG.MDIO_BOARD_INTERFACE string false Custom
CONFIG.MII_IO string false true
CONFIG.M_AXIS_RX.INSERT_VIP string false 0
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64 changes: 27 additions & 37 deletions firmware/FT0/FTM_TCM/xdc/FIT_GBT_kc705_io.xdc
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Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,9 @@ set_property PACKAGE_PIN B25 [get_ports FMC_HPC_clk_A_n]

set_property PACKAGE_PIN H24 [get_ports LAS_EN]
set_property IOSTANDARD LVCMOS25 [get_ports LAS_EN]
set_property IOSTANDARD LVCMOS25 [get_ports SCOPE]
set_property PACKAGE_PIN E28 [get_ports SCOPE]


#set_property PACKAGE_PIN AG27 [get_ports TCM_TT0_P]
#set_property PACKAGE_PIN AJ26 [get_ports TCM_TA1_P]
Expand Down Expand Up @@ -103,8 +106,6 @@ set_property PACKAGE_PIN AF28 [get_ports {LA[0]}]

# ============================================================

set_property IOSTANDARD LVCMOS25 [get_ports SCOPE]
set_property PACKAGE_PIN E28 [get_ports SCOPE]

set_property IOSTANDARD LVDS_25 [get_ports LAS_D_N]
set_property IOSTANDARD LVDS_25 [get_ports LAS_D_P]
Expand Down Expand Up @@ -148,8 +149,8 @@ set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_3]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_2]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_4]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_6]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_7]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_BUTTON_SW_C]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_7]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_BUTTON_SW_C]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_5]
#set_property IOSTANDARD LVCMOS25 [get_ports GPIO_SMA_J13]
#set_property IOSTANDARD LVCMOS25 [get_ports GPIO_SMA_J14]
Expand Down Expand Up @@ -249,36 +250,25 @@ set_property PACKAGE_PIN Y29 [get_ports GPIO_DIP_SW0]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_DIP_SW0]


set_property MARK_DEBUG true [get_nets IsRxData_rxclk_from_GBT]
connect_debug_port u_ila_0/probe1 [get_nets [list IsRxData_rxclk_from_GBT]]

create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 3 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list CDMClkpllcomp/inst/CLK_OUT1_40]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 80 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {Data_from_FITrd[0]} {Data_from_FITrd[1]} {Data_from_FITrd[2]} {Data_from_FITrd[3]} {Data_from_FITrd[4]} {Data_from_FITrd[5]} {Data_from_FITrd[6]} {Data_from_FITrd[7]} {Data_from_FITrd[8]} {Data_from_FITrd[9]} {Data_from_FITrd[10]} {Data_from_FITrd[11]} {Data_from_FITrd[12]} {Data_from_FITrd[13]} {Data_from_FITrd[14]} {Data_from_FITrd[15]} {Data_from_FITrd[16]} {Data_from_FITrd[17]} {Data_from_FITrd[18]} {Data_from_FITrd[19]} {Data_from_FITrd[20]} {Data_from_FITrd[21]} {Data_from_FITrd[22]} {Data_from_FITrd[23]} {Data_from_FITrd[24]} {Data_from_FITrd[25]} {Data_from_FITrd[26]} {Data_from_FITrd[27]} {Data_from_FITrd[28]} {Data_from_FITrd[29]} {Data_from_FITrd[30]} {Data_from_FITrd[31]} {Data_from_FITrd[32]} {Data_from_FITrd[33]} {Data_from_FITrd[34]} {Data_from_FITrd[35]} {Data_from_FITrd[36]} {Data_from_FITrd[37]} {Data_from_FITrd[38]} {Data_from_FITrd[39]} {Data_from_FITrd[40]} {Data_from_FITrd[41]} {Data_from_FITrd[42]} {Data_from_FITrd[43]} {Data_from_FITrd[44]} {Data_from_FITrd[45]} {Data_from_FITrd[46]} {Data_from_FITrd[47]} {Data_from_FITrd[48]} {Data_from_FITrd[49]} {Data_from_FITrd[50]} {Data_from_FITrd[51]} {Data_from_FITrd[52]} {Data_from_FITrd[53]} {Data_from_FITrd[54]} {Data_from_FITrd[55]} {Data_from_FITrd[56]} {Data_from_FITrd[57]} {Data_from_FITrd[58]} {Data_from_FITrd[59]} {Data_from_FITrd[60]} {Data_from_FITrd[61]} {Data_from_FITrd[62]} {Data_from_FITrd[63]} {Data_from_FITrd[64]} {Data_from_FITrd[65]} {Data_from_FITrd[66]} {Data_from_FITrd[67]} {Data_from_FITrd[68]} {Data_from_FITrd[69]} {Data_from_FITrd[70]} {Data_from_FITrd[71]} {Data_from_FITrd[72]} {Data_from_FITrd[73]} {Data_from_FITrd[74]} {Data_from_FITrd[75]} {Data_from_FITrd[76]} {Data_from_FITrd[77]} {Data_from_FITrd[78]} {Data_from_FITrd[79]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 80 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {FitGbtPrg/RX_Data_DataClk[0]} {FitGbtPrg/RX_Data_DataClk[1]} {FitGbtPrg/RX_Data_DataClk[2]} {FitGbtPrg/RX_Data_DataClk[3]} {FitGbtPrg/RX_Data_DataClk[4]} {FitGbtPrg/RX_Data_DataClk[5]} {FitGbtPrg/RX_Data_DataClk[6]} {FitGbtPrg/RX_Data_DataClk[7]} {FitGbtPrg/RX_Data_DataClk[8]} {FitGbtPrg/RX_Data_DataClk[9]} {FitGbtPrg/RX_Data_DataClk[10]} {FitGbtPrg/RX_Data_DataClk[11]} {FitGbtPrg/RX_Data_DataClk[12]} {FitGbtPrg/RX_Data_DataClk[13]} {FitGbtPrg/RX_Data_DataClk[14]} {FitGbtPrg/RX_Data_DataClk[15]} {FitGbtPrg/RX_Data_DataClk[16]} {FitGbtPrg/RX_Data_DataClk[17]} {FitGbtPrg/RX_Data_DataClk[18]} {FitGbtPrg/RX_Data_DataClk[19]} {FitGbtPrg/RX_Data_DataClk[20]} {FitGbtPrg/RX_Data_DataClk[21]} {FitGbtPrg/RX_Data_DataClk[22]} {FitGbtPrg/RX_Data_DataClk[23]} {FitGbtPrg/RX_Data_DataClk[24]} {FitGbtPrg/RX_Data_DataClk[25]} {FitGbtPrg/RX_Data_DataClk[26]} {FitGbtPrg/RX_Data_DataClk[27]} {FitGbtPrg/RX_Data_DataClk[28]} {FitGbtPrg/RX_Data_DataClk[29]} {FitGbtPrg/RX_Data_DataClk[30]} {FitGbtPrg/RX_Data_DataClk[31]} {FitGbtPrg/RX_Data_DataClk[32]} {FitGbtPrg/RX_Data_DataClk[33]} {FitGbtPrg/RX_Data_DataClk[34]} {FitGbtPrg/RX_Data_DataClk[35]} {FitGbtPrg/RX_Data_DataClk[36]} {FitGbtPrg/RX_Data_DataClk[37]} {FitGbtPrg/RX_Data_DataClk[38]} {FitGbtPrg/RX_Data_DataClk[39]} {FitGbtPrg/RX_Data_DataClk[40]} {FitGbtPrg/RX_Data_DataClk[41]} {FitGbtPrg/RX_Data_DataClk[42]} {FitGbtPrg/RX_Data_DataClk[43]} {FitGbtPrg/RX_Data_DataClk[44]} {FitGbtPrg/RX_Data_DataClk[45]} {FitGbtPrg/RX_Data_DataClk[46]} {FitGbtPrg/RX_Data_DataClk[47]} {FitGbtPrg/RX_Data_DataClk[48]} {FitGbtPrg/RX_Data_DataClk[49]} {FitGbtPrg/RX_Data_DataClk[50]} {FitGbtPrg/RX_Data_DataClk[51]} {FitGbtPrg/RX_Data_DataClk[52]} {FitGbtPrg/RX_Data_DataClk[53]} {FitGbtPrg/RX_Data_DataClk[54]} {FitGbtPrg/RX_Data_DataClk[55]} {FitGbtPrg/RX_Data_DataClk[56]} {FitGbtPrg/RX_Data_DataClk[57]} {FitGbtPrg/RX_Data_DataClk[58]} {FitGbtPrg/RX_Data_DataClk[59]} {FitGbtPrg/RX_Data_DataClk[60]} {FitGbtPrg/RX_Data_DataClk[61]} {FitGbtPrg/RX_Data_DataClk[62]} {FitGbtPrg/RX_Data_DataClk[63]} {FitGbtPrg/RX_Data_DataClk[64]} {FitGbtPrg/RX_Data_DataClk[65]} {FitGbtPrg/RX_Data_DataClk[66]} {FitGbtPrg/RX_Data_DataClk[67]} {FitGbtPrg/RX_Data_DataClk[68]} {FitGbtPrg/RX_Data_DataClk[69]} {FitGbtPrg/RX_Data_DataClk[70]} {FitGbtPrg/RX_Data_DataClk[71]} {FitGbtPrg/RX_Data_DataClk[72]} {FitGbtPrg/RX_Data_DataClk[73]} {FitGbtPrg/RX_Data_DataClk[74]} {FitGbtPrg/RX_Data_DataClk[75]} {FitGbtPrg/RX_Data_DataClk[76]} {FitGbtPrg/RX_Data_DataClk[77]} {FitGbtPrg/RX_Data_DataClk[78]} {FitGbtPrg/RX_Data_DataClk[79]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 1 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list FitGbtPrg/RX_IsData_DataClk]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 1 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list IsData_from_FITrd]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets GPIO_SMA_J13_OBUF]
set_property OFFCHIP_TERM NONE [get_ports GPIO_SMA_J13]
set_property OFFCHIP_TERM NONE [get_ports TCM_SPI_MOSI]
set_property OFFCHIP_TERM NONE [get_ports TCM_SPI_SCK]
set_property OFFCHIP_TERM NONE [get_ports TCM_SPI_SEL]
set_property OFFCHIP_TERM NONE [get_ports LA[15]]
set_property OFFCHIP_TERM NONE [get_ports LA[14]]
set_property OFFCHIP_TERM NONE [get_ports LA[13]]
set_property OFFCHIP_TERM NONE [get_ports LA[12]]
set_property OFFCHIP_TERM NONE [get_ports LA[11]]
set_property OFFCHIP_TERM NONE [get_ports LA[10]]
set_property OFFCHIP_TERM NONE [get_ports LA[9]]
set_property OFFCHIP_TERM NONE [get_ports LA[8]]
set_property OFFCHIP_TERM NONE [get_ports LA[7]]
set_property OFFCHIP_TERM NONE [get_ports LA[6]]
set_property OFFCHIP_TERM NONE [get_ports LA[5]]
set_property OFFCHIP_TERM NONE [get_ports LA[4]]
set_property OFFCHIP_TERM NONE [get_ports LA[3]]
set_property OFFCHIP_TERM NONE [get_ports LA[2]]
set_property OFFCHIP_TERM NONE [get_ports LA[1]]
set_property OFFCHIP_TERM NONE [get_ports LA[0]]
set_property OFFCHIP_TERM NONE [get_ports sfp_rate_sel[1]]
set_property OFFCHIP_TERM NONE [get_ports sfp_rate_sel[0]]
2 changes: 1 addition & 1 deletion firmware/FT0/PM/make.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -244,7 +244,7 @@ if {[string equal $proj_create "yes"]} {
set_property -name "processing_order" -value "EARLY" -objects $file_obj

set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*/xdc/ios.xdc"]]
set_property -name "processing_order" -value "EARLY" -objects $file_obj
set_property -name "processing_order" -value "NORMAL" -objects $file_obj

# Set 'constrs_1' fileset properties
set obj [get_filesets constrs_1]
Expand Down
12 changes: 6 additions & 6 deletions firmware/FT0/TCM/hdl/tcm.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -168,7 +168,7 @@ signal clksys40 : std_logic;
signal CSi, MOSIi, MISOi, SCKi : STD_LOGIC;
signal bitcnt_A, bitcnt_C : STD_LOGIC_VECTOR (2 downto 0);
signal Tcnt_cnt : STD_LOGIC_VECTOR (3 downto 0);
signal Thigh, Tlow : STD_LOGIC_VECTOR (8 downto 0);
signal Thigh, Tlow : STD_LOGIC_VECTOR (9 downto 0);
signal Tdiff : STD_LOGIC_VECTOR (9 downto 0);
signal selai, selci, sckai, sckci, mosiai, mosici, misoai, misoci, reqA, reqC, reqA2, reqA1, reqA0, reqC2, reqC1, reqC0 : STD_LOGIC_VECTOR (9 downto 0);
signal PM_rq : STD_LOGIC_VECTOR (19 downto 0);
Expand Down Expand Up @@ -411,9 +411,9 @@ end component;
-- FIT readour status, including BCOR_ID to PM/TCM
FIT_GBT_status_O : out FIT_GBT_status_type;
rx_ph320 : out std_logic_vector(2 downto 0);
ph_error320 : out std_logic;
ph_error320 : out std_logic

GPIO_O : out std_logic_vector(15 downto 0)
--GPIO_O : out std_logic_vector(15 downto 0)
);
end component;
-- ###############################################
Expand Down Expand Up @@ -1269,8 +1269,8 @@ spi_wr2<=spi_wr1; spi_wr1<=spi_wr0; spi_wr0<=spi_wr_rdy;

if (spi_wr_req='1') or (tcmr_wr='1') then
case Treg_addr is
when "000" => Tlow<=Treg_data(8 downto 0);
when "001" => Thigh<=Treg_data(8 downto 0);
when "000" => Tlow<=Treg_data(9 downto 0);
when "001" => Thigh<=Treg_data(9 downto 0);
when "010" => SC_A<=Treg_data;
when "011" => SC_C<=Treg_data;
when "100" => C_A<=Treg_data;
Expand Down Expand Up @@ -1338,7 +1338,7 @@ cou_CC: counter32 port map (clk320=> clk320A, cout=> count_r(12), rd=> cnt_lock
cou_orc: counter32 port map (clk320=> clk320A, cout=> count_r(13), rd=> cnt_lock, clr=> cnt_clr, inc=> bg_Orclr);
cou_andc: counter32 port map (clk320=> clk320A, cout=> count_r(14), rd=> cnt_lock, clr=> cnt_clr, inc=> bg_Andclr);

Vertex_0<= '1' when ((signed(Tdiff(8 downto 0))>=signed(Tlow)) and (signed(Tdiff(8 downto 0))<=signed(Thigh)) and (Tdiff(9)=Tdiff(8)) and (OrA_i='1') and (OrC_i='1')) else '0';
Vertex_0<= '1' when (signed(Tdiff)>=signed(Tlow)) and (signed(Tdiff)<=signed(Thigh)) and (OrA_i='1') and (OrC_i='1') else '0';

AmplS<= (AmplA(16) & AmplA) + (AmplC(16) & AmplC);

Expand Down
2 changes: 1 addition & 1 deletion firmware/FT0/TCM/ipcore_properties/gig_ethernet_pcs_pma_0.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,7 @@ CONFIG.SGMII_PHY_Mode string false false
CONFIG.S_AXI.INSERT_VIP string false 0
CONFIG.S_AXI_ACLK.INSERT_VIP string false 0
CONFIG.S_AXI_RESETN.INSERT_VIP string false 0
CONFIG.Standard string false 1000BASEX
CONFIG.Standard string false BOTH
CONFIG.SupportLevel string false Include_Shared_Logic_in_Example_Design
CONFIG.TXOUTCLK_PORT.INSERT_VIP string false 0
CONFIG.Timer_Format string false Time_of_day
Expand Down
2 changes: 1 addition & 1 deletion firmware/FT0/TCM/ipcore_properties/tri_mode_ethernet_mac_0.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ CONFIG.GTX_CLK_OUT.INSERT_VIP string false 0
CONFIG.Half_Duplex string false false
CONFIG.Int_Clk_Src string false user_clk2
CONFIG.Int_Mode_Type string false BASEX
CONFIG.MAC_Speed string false 1000_Mbps
CONFIG.MAC_Speed string false Tri_speed
CONFIG.MDIO_BOARD_INTERFACE string false Custom
CONFIG.MII_IO string false true
CONFIG.M_AXIS_RX.INSERT_VIP string false 0
Expand Down
16 changes: 14 additions & 2 deletions firmware/FT0/TCM/make.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -263,14 +263,26 @@ if {[string equal $proj_create "yes"]} {
}

# Add/Import constrs file and set constrs file properties
set file "[file normalize "$origin_dir/xdc/tcm.xdc"]"
add_files -fileset constrs_1 [list $file]

set file "[file normalize "$origin_dir/xdc/tcm_pins.xdc"]"
add_files -fileset constrs_1 [list $file]
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "$origin_dir/xdc/tcm_pins.xdc"]]
set_property -name "processing_order" -value "EARLY" -objects $file_obj


set file "[file normalize "$origin_dir/xdc/tcm.xdc"]"
add_files -fileset constrs_1 [list $file]
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "$origin_dir/xdc/tcm.xdc"]]
set_property -name "processing_order" -value "NORMAL" -objects $file_obj



set file "[file normalize "$origin_dir/xdc/timing.xdc"]"
add_files -fileset constrs_1 [list $file]
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "$origin_dir/xdc/Timing.xdc"]]
set_property -name "used_in" -value "implementation" -objects $file_obj
set_property -name "used_in_synthesis" -value "0" -objects $file_obj


set_property -name "file_type" -value "XDC" -objects [get_files -of_objects [get_filesets constrs_1] [list "*/xdc/*.xdc"]]

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