release 1.1 calib hists in fpga (#19)

- calibration histograms available in fpga
- HDMI sync fix
- auto HDMI resync after HDMI reset
- bit files added to git
- FTM mac addr changed
- TCM SPI reset bug fixed
- trailers removed from RDH packets

firmware/FT0/PM/hdl/PM12_pkg.vhd

@@ -0,0 +1,9 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+package PM12_pkg is
+type trig_time is array (0 to 11)  of STD_LOGIC_VECTOR (9 downto 0);
+type trig_ampl0 is array (0 to 11) of STD_LOGIC_VECTOR(12 downto 0);
+type hyst_vector is array (0 to 11) of STD_LOGIC_VECTOR(25 downto 0);
+end package; 

firmware/FT0/PM/hdl/autophase.vhd

@@ -77,16 +77,20 @@ if (lock_i='0') then ms_cou <=(others=>'0'); state <=(others=>'0'); j_cou <=(oth
 if (t1ms='1') then ms_cou <=(others=>'0'); j_cou <=(others=>'0'); 
 
  case to_integer(unsigned(state)) is
-    when 0 => if (j_cou>=10) then state<="001"; dir<='1'; end if; 
-              if (m0="100100") then  state<="110"; dir<='1'; end if;
+    when 0 => if (j_cou>=10)  then state<="001"; dir<='1';  
+                 else
+                  if (m0="100000") then  state<="110"; dir<='1'; end if;
+              end if;
     when 1 => if (j_cou=0)  then state<="010"; ml<= m0; end if;
     when 2 => if (m0=(ml+"000111")) then  state<="011"; end if;
-    when 3 => if (j_cou>=10) then state<="100"; dir<='0'; end if;
-              if (m0="011100") then  state<="110"; dir<='0'; end if;
+    when 3 => if (j_cou>=10) then state<="100"; dir<='0';
+                else 
+                 if (m0="011111") then  state<="111"; dir<='0'; end if;
+              end if;
     when 4 => if (j_cou=0)  then state<="101"; ml<= mh0(5) & mh0(5 downto 1); end if;
     when 5 => if (m0=ml) then done_i<='1'; end if;
-    when 6 => if (m0=0) then  state<="000";  dir<='0'; end if;
-    when others=> null;
+    when 6 => if (signed(m0)=10) then  state<="000";  dir<='0'; end if;
+    when 7 => if (signed(m0)=-10) then  state<="000"; end if;
  end case;
 
 else 

firmware/FT0/PM/hdl/hyst.vhd

@@ -0,0 +1,214 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 01/22/2021 07:40:08 PM
+-- Design Name: 
+-- Module Name: hyst - RTL
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+library work;
+use work.PM12_pkg.all; 
+
+
+entity hyst is
+  Port ( 
+        clk320 : in std_logic;
+        hyst_inp_data : in hyst_vector;
+        hyst_a : in std_logic_vector(11 downto 0);
+        hyst_t : in std_logic_vector(11 downto 0);
+        hyst_st : in std_logic;
+        cnt_clr : in std_logic;
+        busy : out std_logic;
+        hyst_addr_i : in std_logic_vector(16 downto 0);
+        hyst_addr_o : out std_logic_vector(16 downto 0);
+        wr_addr : in std_logic;
+        hyst_data_o : out std_logic_vector(31 downto 0);
+        n_addr : in std_logic;
+        lock320 : in std_logic;
+        stp : out std_logic
+  );
+end hyst;
+
+architecture RTL of hyst is
+
+type data1_vect is array (0 to 11) of STD_LOGIC_VECTOR (0 downto 0);
+type data9_vect is array (0 to 11) of STD_LOGIC_VECTOR (8 downto 0);
+type data13_vect is array (0 to 11) of STD_LOGIC_VECTOR (12 downto 0);
+type data16_vect is array (0 to 11) of STD_LOGIC_VECTOR (15 downto 0);
+type data32_vect is array (0 to 11) of STD_LOGIC_VECTOR (31 downto 0);
+
+signal wr_mem_t, wr_mem_a, wr_mem_an : data1_vect;
+signal t_in, t_out, a_in, a_out, an_in, an_out : data16_vect;
+signal loc_addr :  std_logic_vector (16 downto 0);
+signal t_rd, a_rd, an_rd : data32_vect;
+signal ampln_addr : data9_vect;
+signal ampl_addr : data13_vect;
+signal clr, lock : std_logic;
+signal wr_b :  std_logic_vector (0 downto 0);
+signal hyst_a0, hyst_a1, hyst_a2, hyst_t0, hyst_t1, hyst_t2, ovf : std_logic_vector (11 downto 0);
+signal hyst_data : hyst_vector;
+
+COMPONENT hyst_mem4k
+  PORT (
+    clka : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    regceb : IN STD_LOGIC;
+    web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+    dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+  );
+END COMPONENT;
+
+COMPONENT hyst_mem8k
+  PORT (
+    clka : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    regceb : IN STD_LOGIC;
+    web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+    dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+  );
+END COMPONENT;
+
+COMPONENT hyst_mem512
+  PORT (
+    clka : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    regceb : IN STD_LOGIC;
+    web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+  );
+END COMPONENT;
+
+begin
+
+busy<= clr; hyst_addr_o <= loc_addr; lock<= not lock320;
+
+hyst_data_o<= a_rd(to_integer(unsigned(loc_addr(16 downto 13))))   when (loc_addr(12) = '0') else
+              t_rd(to_integer(unsigned(loc_addr(16 downto 13))))  when (loc_addr(12 downto 11) = "10") else
+              an_rd(to_integer(unsigned(loc_addr(16 downto 13))));
+
+ stp<='1' when (ovf/=0)  else '0';               
+
+mem: for i in 0 to 11 generate
+
+mem4k: hyst_mem4k port map (clka =>clk320, wea=>wr_mem_t(i), addra => hyst_data(i)(11 downto 0), dina =>t_in(i), douta => t_out(i), clkb =>clk320, regceb =>lock, web =>wr_b, addrb=> loc_addr(10 downto 0), dinb=> (others=>'0'), doutb => t_rd(i)); 
+mem8k: hyst_mem8k port map (clka =>clk320, wea=>wr_mem_a(i), addra => ampl_addr(i), dina =>a_in(i), douta => a_out(i), clkb =>clk320, regceb =>lock, web => wr_b, addrb=> loc_addr(11 downto 0), dinb=> (others=>'0'), doutb => a_rd(i)); 
+mem512: hyst_mem512 port map (clka =>clk320, wea=>wr_mem_an(i), addra => ampln_addr(i), dina =>an_in(i), douta => an_out(i), clkb =>clk320, regceb =>lock, web => wr_b, addrb=> loc_addr(7 downto 0), dinb=> (others=>'0'), doutb => an_rd(i)); 
+
+ampln_addr(i) <=  hyst_data(i)(25) & (not  hyst_data(i)(19 downto 12));
+ampl_addr(i) <=  hyst_data(i)(25) & hyst_data(i)(23 downto 12);
+wr_b(0)<=clr;
+
+
+t_in(i)<=  x"FFFF" when (t_out(i)=x"FFFF") else
+           t_out(i)+1;
+
+a_in(i)<=  x"FFFF" when (a_out(i)=x"FFFF") else
+           a_out(i)+1;
+
+an_in(i)<= x"FFFF" when (an_out(i)=x"FFFF") else
+           an_out(i)+1;
+
+
+wr_mem_t(i)(0)<= hyst_t2(i);
+wr_mem_a(i)(0)<= hyst_a2(i) and (not hyst_data(i)(24));
+wr_mem_an(i)(0)<=hyst_a2(i) and hyst_data(i)(24);
+
+end generate;
+
+
+process (clk320)
+begin
+if (clk320'event and clk320='1') then
+
+if (hyst_st='1') then hyst_t0<= hyst_t and (not hyst_t1);
+  else hyst_t0<=(others=>'0');
+end if;
+
+hyst_t2<= hyst_t1; hyst_t1<= hyst_t0;
+
+if (hyst_st='1') then hyst_a0<= hyst_a and (not hyst_a1);
+  else hyst_a0<=(others=>'0');
+end if;
+
+hyst_a2<= hyst_a1; hyst_a1<= hyst_a0; 
+
+for i in 0 to 11 loop
+
+if (hyst_st='1') and  (hyst_t1(i)='0') then hyst_data(i)(11 downto 0) <= hyst_inp_data(i)(11 downto 0); end if; 
+if (hyst_st='1') and  (hyst_a1(i)='0') then hyst_data(i)(25 downto 12) <= hyst_inp_data(i)(25 downto 12); end if;
+if ((t_out(i)>=x"FFFE") and (wr_mem_t(i)(0)='1')) or ((a_out(i)>=x"FFFE") and (wr_mem_a(i)(0)='1')) or ((an_out(i)>=x"FFFE") and (wr_mem_an(i)(0)='1')) then ovf(i)<= '1' ; else ovf(i)<= '0'; end if;
+end loop;
+
+if (cnt_clr='1') then clr <='1'; 
+   else 
+   if (loc_addr(11 downto 0) = x"FFF") then clr<='0'; end if;
+end if; 
+
+if (cnt_clr='1') then loc_addr(11 downto 0)<= (others=>'0');
+ else
+  if (clr='1') then loc_addr(11 downto 0)<= loc_addr(11 downto 0)+1; 
+    else
+     if (wr_addr='1') then loc_addr<=hyst_addr_i;
+       else 
+       if (n_addr='1') then 
+       if (loc_addr(12 downto 0)>='1' & x"8ff") then 
+         loc_addr(12 downto 0)<=(others=>'0'); 
+         if (loc_addr(16 downto 13)<11) then loc_addr(16 downto 13)<= loc_addr(16 downto 13)+1;
+          else loc_addr(16 downto 13)<=x"0";
+         end if;
+        else
+         loc_addr(12 downto 0)<=loc_addr(12 downto 0)+1;
+       end if; 
+      end if;
+     end if;
+  end if;
+end if;
+
+end if;
+end process;
+
+end RTL;

firmware/FT0/PM/hdl/trigger.vhd

@@ -17,15 +17,6 @@
 -- Additional Comments:
 -- 
 ----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-package PM12_pkg is
-type trig_time is array (0 to 11)  of STD_LOGIC_VECTOR (9 downto 0);
-type trig_ampl0 is array (0 to 11) of STD_LOGIC_VECTOR(12 downto 0);
-end package; 
-
-
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;

firmware/FT0/PM/ipcore_properties/hyst_mem4k.txt

@@ -0,0 +1,78 @@
+Property                                           Type    Read-only  Value
+CONFIG.AXILITE_SLAVE_S_AXI.INSERT_VIP              string  false      0
+CONFIG.AXI_ID_Width                                string  false      4
+CONFIG.AXI_SLAVE_S_AXI.INSERT_VIP                  string  false      0
+CONFIG.AXI_Slave_Type                              string  false      Memory_Slave
+CONFIG.AXI_Type                                    string  false      AXI4_Full
+CONFIG.Additional_Inputs_for_Power_Estimation      string  false      false
+CONFIG.Algorithm                                   string  false      Minimum_Area
+CONFIG.Assume_Synchronous_Clk                      string  false      true
+CONFIG.Byte_Size                                   string  false      9
+CONFIG.CLK.ACLK.INSERT_VIP                         string  false      0
+CONFIG.CTRL_ECC_ALGO                               string  false      NONE
+CONFIG.Coe_File                                    string  false      no_coe_file_loaded
+CONFIG.Collision_Warnings                          string  false      ALL
+CONFIG.Component_Name                              string  false      hyst_mem4k
+CONFIG.Disable_Collision_Warnings                  string  false      false
+CONFIG.Disable_Out_of_Range_Warnings               string  false      false
+CONFIG.ECC                                         string  false      false
+CONFIG.EN_DEEPSLEEP_PIN                            string  false      false
+CONFIG.EN_ECC_PIPE                                 string  false      false
+CONFIG.EN_SAFETY_CKT                               string  false      false
+CONFIG.EN_SHUTDOWN_PIN                             string  false      false
+CONFIG.EN_SLEEP_PIN                                string  false      false
+CONFIG.Enable_32bit_Address                        string  false      false
+CONFIG.Enable_A                                    string  false      Always_Enabled
+CONFIG.Enable_B                                    string  false      Always_Enabled
+CONFIG.Error_Injection_Type                        string  false      Single_Bit_Error_Injection
+CONFIG.Fill_Remaining_Memory_Locations             string  false      false
+CONFIG.Interface_Type                              string  false      Native
+CONFIG.Load_Init_File                              string  false      false
+CONFIG.MEM_FILE                                    string  false      no_mem_loaded
+CONFIG.Memory_Type                                 string  false      True_Dual_Port_RAM
+CONFIG.Operating_Mode_A                            string  false      READ_FIRST
+CONFIG.Operating_Mode_B                            string  false      READ_FIRST
+CONFIG.Output_Reset_Value_A                        string  false      0
+CONFIG.Output_Reset_Value_B                        string  false      0
+CONFIG.PRIM_type_to_Implement                      string  false      BRAM
+CONFIG.Pipeline_Stages                             string  false      0
+CONFIG.Port_A_Clock                                string  false      100
+CONFIG.Port_A_Enable_Rate                          string  false      100
+CONFIG.Port_A_Write_Rate                           string  false      50
+CONFIG.Port_B_Clock                                string  false      100
+CONFIG.Port_B_Enable_Rate                          string  false      100
+CONFIG.Port_B_Write_Rate                           string  false      50
+CONFIG.Primitive                                   string  false      8kx2
+CONFIG.RD_ADDR_CHNG_A                              string  false      false
+CONFIG.RD_ADDR_CHNG_B                              string  false      false
+CONFIG.READ_LATENCY_A                              string  false      1
+CONFIG.READ_LATENCY_B                              string  false      1
+CONFIG.RST.ARESETN.INSERT_VIP                      string  false      0
+CONFIG.Read_Width_A                                string  false      16
+CONFIG.Read_Width_B                                string  false      32
+CONFIG.Register_PortA_Output_of_Memory_Core        string  false      false
+CONFIG.Register_PortA_Output_of_Memory_Primitives  string  false      true
+CONFIG.Register_PortB_Output_of_Memory_Core        string  false      false
+CONFIG.Register_PortB_Output_of_Memory_Primitives  string  false      true
+CONFIG.Remaining_Memory_Locations                  string  false      0
+CONFIG.Reset_Memory_Latch_A                        string  false      false
+CONFIG.Reset_Memory_Latch_B                        string  false      false
+CONFIG.Reset_Priority_A                            string  false      CE
+CONFIG.Reset_Priority_B                            string  false      CE
+CONFIG.Reset_Type                                  string  false      SYNC
+CONFIG.Use_AXI_ID                                  string  false      false
+CONFIG.Use_Byte_Write_Enable                       string  false      false
+CONFIG.Use_Error_Injection_Pins                    string  false      false
+CONFIG.Use_REGCEA_Pin                              string  false      false
+CONFIG.Use_REGCEB_Pin                              string  false      true
+CONFIG.Use_RSTA_Pin                                string  false      false
+CONFIG.Use_RSTB_Pin                                string  false      false
+CONFIG.Write_Depth_A                               string  false      4096
+CONFIG.Write_Width_A                               string  false      16
+CONFIG.Write_Width_B                               string  false      32
+CONFIG.ecctype                                     string  false      No_ECC
+CONFIG.register_porta_input_of_softecc             string  false      false
+CONFIG.register_portb_output_of_softecc            string  false      false
+CONFIG.softecc                                     string  false      false
+CONFIG.use_bram_block                              string  false      Stand_Alone
+IPDEF                                              string  true       xilinx.com:ip:blk_mem_gen:8.4