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1. YASA YASA Public

   🐌Yet Another Simulation Architecture

   Python 73 37

2. YasaUvk YasaUvk Public

   🐛UVM verification kits which uses YASA as simulation script

   SystemVerilog 13 4

3. Open_RegModel Open_RegModel Public

   🐥Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.

   Verilog 66 26

4. SystemRDL/PeakRDL-uvm SystemRDL/PeakRDL-uvm Public

   Generate UVM register model from compiled SystemRDL input

   Python 51 29

5. uvm_candy_lover uvm_candy_lover Public

   🍬UVM candy lover testbench which uses YASA as simulation script

   SystemVerilog 15 6

6. my_vimrc my_vimrc Public

   🐲Jude's vimrc for DV work(fine tuning for SV/UVM)

   Vim Script 17 10