Advanced FPGA Logic Design

A Project Repository for CPE 166 - Advanced FPGA Logic Design in SystemVerilog, Verilog, and VHDL.

All of the code in this repo roughly follows the lowRISC Verilog Coding Style Guide.

The FPGA development board used for these projects is the Terasic DE10-Lite. A copy-paste pin number file is included in the main directory of the project.

TODO:

• Fix Lab2Part3 Mealy output timing
• Add top files to modules that were altered for demo purposes and remove the demo functionality from the functional module itself so that it can actually be used in other designs.
  • Lab2Part2
  • Lab3Part3
• Improve adherance to style guide
  • Lab3Part1