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wfeldt · Mar 16, 2009 · b9a1b5f · b9a1b5f
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commit b9a1b5f
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Showing 28 changed files with 28 additions and 28 deletions.
diff --git a/test/0001_00_add.done b/test/0001_00_add.done
@@ -29,7 +29,7 @@
 0006a800: *66
 
 ; - - registers
-tsc=0000000000000022
+msr[0010]    0000000000000022 ; tsc
 
 cr0=00000000 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0002_8e_mov_sr.done b/test/0002_8e_mov_sr.done
@@ -6,7 +6,7 @@
 00008ff0:                                                          01  02
 
 ; - - registers
-tsc=0000000000000008
+msr[0010]    0000000000000008 ; tsc
 
 cr0=00000000 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0003_lds_real.done b/test/0003_lds_real.done
@@ -7,7 +7,7 @@
 00002020:  5b  34  d5  eb  1b  d8
 
 ; - - registers
-tsc=0000000000000004
+msr[0010]    0000000000000004 ; tsc
 
 cr0=00000000 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0004_stack32_real.done b/test/0004_stack32_real.done
@@ -4,7 +4,7 @@
 fffffff0:                                                  72  ff  2a  23
 
 ; - - registers
-tsc=0000000000000003
+msr[0010]    0000000000000003 ; tsc
 
 cr0=00000000 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0005_stack16_real.done b/test/0005_stack16_real.done
@@ -4,7 +4,7 @@
 0000fff0:                                                  73  1f  11  02
 
 ; - - registers
-tsc=0000000000000003
+msr[0010]    0000000000000003 ; tsc
 
 cr0=00000000 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0006_div0.done b/test/0006_div0.done
@@ -5,7 +5,7 @@
 0000fff0:                                          50  00  00  01  02  00
 
 ; - - registers
-tsc=0000000000000007
+msr[0010]    0000000000000007 ; tsc
 
 cr0=00000000 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0007_seg_load_pm16.done b/test/0007_seg_load_pm16.done
@@ -7,7 +7,7 @@
 0000fff0:                          18  00  00  00  0c  00  08  00  02  00
 
 ; - - registers
-tsc=0000000000000003
+msr[0010]    0000000000000003 ; tsc
 
 cr0=00000001 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0008_seg_load_pm32.done b/test/0008_seg_load_pm32.done
@@ -8,7 +8,7 @@
 0000fff0:  18  00  00  00  0d  00  00  00  08  00  00  00  02  00  00  00
 
 ; - - registers
-tsc=0000000000000003
+msr[0010]    0000000000000003 ; tsc
 
 cr0=00000001 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0009_loop32.done b/test/0009_loop32.done
@@ -5,7 +5,7 @@
 00002010:  ff  ff  00  00  00  93  cf  00
 
 ; - - registers
-tsc=0000000000000022
+msr[0010]    0000000000000022 ; tsc
 
 cr0=00000001 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0010_loop16.done b/test/0010_loop16.done
@@ -5,7 +5,7 @@
 00002010:  ff  ff  00  00  00  93  cf  00
 
 ; - - registers
-tsc=0000000000000022
+msr[0010]    0000000000000022 ; tsc
 
 cr0=00000001 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0011_jmp_short_cc.done b/test/0011_jmp_short_cc.done
@@ -14,7 +14,7 @@
 000010b0:  38  e9  7f  02  b0  01  fe  c4  f4
 
 ; - - registers
-tsc=0000000000000046
+msr[0010]    0000000000000046 ; tsc
 
 cr0=00000000 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0012_jmp_near_cc.done b/test/0012_jmp_near_cc.done
@@ -17,7 +17,7 @@
 000010e0:  02  00  b0  01  fe  c4  f4
 
 ; - - registers
-tsc=0000000000000046
+msr[0010]    0000000000000046 ; tsc
 
 cr0=00000000 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0013_add.done b/test/0013_add.done
@@ -9,7 +9,7 @@
 0003fff0:  13  00  17  00  83  00  13  00  97  00  17  08  92  00  07  00
 
 ; - - registers
-tsc=000000000000001f
+msr[0010]    000000000000001f ; tsc
 
 cr0=00000000 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0014_or.done b/test/0014_or.done
@@ -9,7 +9,7 @@
 0003fff0:  86  00  86  00  82  00  86  00  06  00  82  00  86  00  02  00
 
 ; - - registers
-tsc=000000000000001f
+msr[0010]    000000000000001f ; tsc
 
 cr0=00000000 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0015_adc.done b/test/0015_adc.done
@@ -9,7 +9,7 @@
 0003fff0:  07  00  06  00  92  08  82  00  86  00  12  00  92  00  07  00
 
 ; - - registers
-tsc=000000000000001f
+msr[0010]    000000000000001f ; tsc
 
 cr0=00000000 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0016_sbb.done b/test/0016_sbb.done
@@ -9,7 +9,7 @@
 0003fff0:  16  00  87  08  86  00  02  08  06  08  06  00  12  00  87  00
 
 ; - - registers
-tsc=000000000000001f
+msr[0010]    000000000000001f ; tsc
 
 cr0=00000000 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0017_and.done b/test/0017_and.done
@@ -9,7 +9,7 @@
 0003fff0:  02  00  06  00  86  00  02  00  06  00  06  00  86  00  02  00
 
 ; - - registers
-tsc=000000000000001f
+msr[0010]    000000000000001f ; tsc
 
 cr0=00000000 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0018_sub.done b/test/0018_sub.done
@@ -9,7 +9,7 @@
 0003fff0:  02  00  97  08  83  00  93  08  83  00  87  08  92  00  83  00
 
 ; - - registers
-tsc=000000000000001f
+msr[0010]    000000000000001f ; tsc
 
 cr0=00000000 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0019_xor.done b/test/0019_xor.done
@@ -9,7 +9,7 @@
 0003fff0:  82  00  86  00  86  00  82  00  02  00  02  00  82  00  82  00
 
 ; - - registers
-tsc=000000000000001f
+msr[0010]    000000000000001f ; tsc
 
 cr0=00000000 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0020_cmp.done b/test/0020_cmp.done
@@ -9,7 +9,7 @@
 0003fff0:  86  00  16  00  03  00  83  00  06  08  83  00  12  00  86  00
 
 ; - - registers
-tsc=000000000000001f
+msr[0010]    000000000000001f ; tsc
 
 cr0=00000000 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0021_imul_b.done b/test/0021_imul_b.done
@@ -6,7 +6,7 @@
 0003fff0:                  03  08  03  08  03  08  03  08  03  08  03  08
 
 ; - - registers
-tsc=000000000000000d
+msr[0010]    000000000000000d ; tsc
 
 cr0=00000000 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0022_imul_w.done b/test/0022_imul_w.done
@@ -7,7 +7,7 @@
 0003fff0:                  03  08  03  08  03  08  03  08  03  08  03  08
 
 ; - - registers
-tsc=000000000000000d
+msr[0010]    000000000000000d ; tsc
 
 cr0=00000000 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0024_cwd.done b/test/0024_cwd.done
@@ -4,7 +4,7 @@
 0003fff0:                                                  ff  ff  00  00
 
 ; - - registers
-tsc=0000000000000008
+msr[0010]    0000000000000008 ; tsc
 
 cr0=00000000 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0025_cdq.done b/test/0025_cdq.done
@@ -5,7 +5,7 @@
 0003fff0:                                  ff  ff  ff  ff  00  00  00  00
 
 ; - - registers
-tsc=0000000000000008
+msr[0010]    0000000000000008 ; tsc
 
 cr0=00000000 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0026_cbw.done b/test/0026_cbw.done
@@ -4,7 +4,7 @@
 0003fff0:                                                  86  ff  34  00
 
 ; - - registers
-tsc=0000000000000008
+msr[0010]    0000000000000008 ; tsc
 
 cr0=00000000 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0027_cwde.done b/test/0027_cwde.done
@@ -5,7 +5,7 @@
 0003fff0:                                  75  81  ff  ff  68  35  00  00
 
 ; - - registers
-tsc=0000000000000008
+msr[0010]    0000000000000008 ; tsc
 
 cr0=00000000 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0028_movsb.done b/test/0028_movsb.done
@@ -5,7 +5,7 @@
 00040050:  6d  1c  3a  14  bd  ca  7e  5b  41  93  1a  af  55  82  6d  2b
 
 ; - - registers
-tsc=0000000000000006
+msr[0010]    0000000000000006 ; tsc
 
 cr0=00000000 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000

diff --git a/test/0029_movsb_32.done b/test/0029_movsb_32.done
@@ -6,7 +6,7 @@
 90040050:  6e  c7  1b  0b  9b  3a  6e  16  35  f7  b3  a8  fe  71  3f  fe
 
 ; - - registers
-tsc=0000000000000006
+msr[0010]    0000000000000006 ; tsc
 
 cr0=00000000 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
 dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000