Skip to content
View wethmiranasinghe's full-sized avatar

Highlights

  • Pro

Block or report wethmiranasinghe

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. e20-3yp-OceanEyes e20-3yp-OceanEyes Public

    Forked from cepdnaclk/e20-3yp-OceanEyes

    OceanEyes is a Sea Weather and Pollution Monitoring Buoy.

  2. e20-co227-Erasmus-plus-Project-Web-and-MIS e20-co227-Erasmus-plus-Project-Web-and-MIS Public

    Forked from cepdnaclk/e20-co227-Erasmus-plus-Project-Web-and-MIS

    The Erasmus+ Project Web and Management Information System (MIS) is a comprehensive software solution designed to support the management and coordination of Erasmus+ projects. It serves as a centra…

    JavaScript

  3. e20-co543-Low-Light-Image-Enhancement e20-co543-Low-Light-Image-Enhancement Public

    Forked from cepdnaclk/e20-co543-Low-Light-Image-Enhancement

    Low-light image enhancement focuses on improving the quality of images captured in poorly lit conditions, addressing issues like low visibility, noise, and poor contrast.

  4. co222-programming-methodology co222-programming-methodology Public

    This is a course project developed under CO222 Programming Methodology module, focusing on practical applications of algorithms and optimization techniques in complex scenarios using the C programm…

    C

  5. improved-image-dehazing-DIP improved-image-dehazing-DIP Public

    Forked from chamath-n/improved-image-dehazing-DIP

    Improved image dehazing program using the Dark Channel Prior (DCP)

    Python

  6. single-cycle-processor single-cycle-processor Public

    A simple 8-bit single-cycle processor with a memory sub-system designed using Verilog HDL.

    Verilog 2