Development Environment

Red Pitaya

• Running STEMlab verision 0.98-696_stable (https://downloads.redpitaya.com/downloads/STEMlab-125-1x/old/STEMlab_125-xx_OS_0.98-696_stable.img.zip)

Development Machine

• OS: Pop!_OS 19.10 x86_64
• Kernel: 5.3.0-7629-generic
• Shell: bash 5.0.3
• DE: GNOME 3.34.3
• WM: GNOME Shell
• Terminal: gnome-terminal
• CPU: AMD Ryzen 9 3900X 12- (24) @ 3.800GHz
• GPU: NVIDIA GeForce GTX 970
• Memory: 64314MiB

Installation of Vivado

• Downloaded Vivado 2019.2 unified installer from the Xilinx website (requires account)
• Extracted the installer and ran sudo ./Xilinx_Unified_2019.2_1106_2127_Lin64.bin
• Ignored compatibility warning
• For me the installer froze during 'Generating installed device list'
  • Solved by installing sudo apt install libncurses5
  • For reference: https://forums.xilinx.com/t5/Installation-and-Licensing/Vivado-2018-3-Final-Processing-hangs-at-Generating-installed/m-p/972114#M25861

Using pyrpl repository for building

• Clone the pyrpl repository fork https://github.com/npeschke/pyrpl.git
• Switch to the open_fpga_fads branch
  • This contains my changes as well as necessary changes to build with the current Vivado version

Build process

The build process is make based. To run the build follow the instructions of the pyrpl documentation https://pyrpl.readthedocs.io/en/latest/developer_guide/fpga_compilation.html#compiling-the-fpga-code In brief change to the pyrpl/fpga directory and run make.

Build order

After cleaning the output directories, a master TCL script is executed. TCL is a scripting language for automating Vivado. The TCL script includes the entire setup and build of a Vivado project for the pyrpl RedPitaya implementation. It loads the verilog scripts in the pyrpl/fpga/rtl folder (If you add additional scripts they also have to be added in the TCL) and the constraints file which is the link between the physical properties of the components attached to the pins of the FPGA and the way the FPGA drives those pins. Also some clocks are defined there.

After the prerequisites are loaded, the synthesis, implementation and bitstream generation are started. In the end, new bitstreams are generated.

For testing, I am manually copying the pyrpl/fpga/out/red_pitaya_uncompressed.bit file over to the RedPitaya and load it manually.

On my computer

scp pyrpl/fpga/out/red_pitaya_uncompressed.bit  [email protected]:/root/bitstreams/red_pitaya_uncompressed_mem_test.bit

On the RedPitaya

cat /root/bitstreams/red_pitaya_uncompressed_mem_test.bit > /dev/xdevcfg

The bitstream was loaded successfully if the blue LED on the RedPitaya turns on afterwards. Otherwise, restart the RedPitaya by disconnecting the power cable. The bitstream is only loaded temporarily and during restart, the original bitfile will be loaded.