Skip to content

Commit

Permalink
Merge branch 'mapping_to_cgra' into matmul_relu
Browse files Browse the repository at this point in the history
  • Loading branch information
bobcheng15 committed Nov 26, 2023
2 parents 2d9960b + 428033b commit a8cd9a8
Show file tree
Hide file tree
Showing 4 changed files with 165 additions and 15 deletions.
22 changes: 15 additions & 7 deletions compiler/sam-outputs/onyx-dot/matmul_ikj.gv
Original file line number Diff line number Diff line change
Expand Up @@ -18,8 +18,11 @@ digraph SAM {
10 [comment="type=repsiggen,index=j" label="RepeatSignalGenerator j" color=cyan3 shape=box style=filled type="repsiggen" index="j"]
8 [comment="type=arrayvals,tensor=C" label="Array Vals: C" color=green2 shape=box style=filled type="arrayvals" tensor="C"]
14 [comment="type=fiberlookup,index=k,tensor=B,mode=1,format=compressed,src=true,root=false" label="FiberLookup k: B1\ncompressed" color=green4 shape=box style=filled type="fiberlookup" index="k" tensor="B" mode="1" format="compressed" src="true" root="false"]
19 -> 18 [label="crd" style=dashed type="crd" comment=""]
18 -> 17 [label="crd" style=dashed type="crd" comment=""]
23 [comment="type=crddrop,outer=i,inner=j" label="CrdDrop i,j" color=orange shape=box style=filled type="crddrop" outer="i" inner="j"]
#24 [comment="type=fiberlookup,index=i,tensor=B,mode=0,format=compressed,src=true,root=true" label="FiberLookup i: B0\ncompressed" color=green4 shape=box style=filled type="fiberlookup" index="i" tensor="B" mode="0" format="compressed" src="true" root="true"]
19 -> 18 [label="ref" style=bold type="ref" comment="", vr_special="true"]
18 -> 17 [label="ref" style=bold type="ref" comment="", vr_special="true"]
#19 -> 17 [label="crd" style=dashed type="crd" comment=""]
17 -> 16 [label="repsig" style=dotted type="repsig"]
16 -> 15 [label="ref" style=bold type="ref"]
15 -> 13 [label="crd_in-C" style=dashed type="crd" comment="in-C"]
Expand All @@ -28,17 +31,22 @@ digraph SAM {
7 -> 6 [label="val" type="val"]
13 -> 12 [label="ref_out-C" style=bold type="ref" comment="out-C"]
12 -> 11 [label="crd" style=dashed type="crd" comment=""]
19 -> 2 [label="crd_i" style=dashed type="crd" comment="i"]
11 -> 20 [label="crd_j" style=dashed type="crd" comment="j" special="true"]
11 -> 10 [label="crd" style=dashed type="crd" comment=""]
10 -> 9 [label="repsig" style=dotted type="repsig"]
12 -> 8 [label="ref" style=bold type="ref" comment=""]
8 -> 6 [label="val" type="val"]
15 -> 13 [label="ref_in-C" style=bold type="ref" comment="in-C"]
19 -> 14 [label="ref" style=bold type="ref" comment=""]
18 -> 14 [label="ref" style=bold type="ref" comment=""]
14 -> 13 [label="crd_in-B" style=dashed type="crd" comment="in-B"]
14 -> 13 [label="ref_in-B" style=bold type="ref" comment="in-B"]
6 -> 20 [label="mul_val_out" type="val"]
20 -> 0 [label="final_vals" type="val"]
20 -> 1 [label="crd_out-j" style=dashed type="crd" comment="out-j"]
}
20 -> 23 [label="crd_inner-j" style=dashed type="crd" comment="inner-j"]
19 -> 23 [label="crd_outer-i" style=dashed type="crd" comment="outer-i" special="true"]
#18 -> 23 [label="crd_outer-i" style=dashed type="crd" comment="outer-i" special="true"]
#18 -> 2 [label="crd_out-i" style=dashed type="crd" comment="out-i"]
23 -> 2 [label="crd_outer-i" style=dashed type="crd" comment="outer-i"]
23 -> 1 [label="crd_inner-j" style=dashed type="crd" comment="inner-j"]
#20 -> 1[label="final_crd-j" style=dashed type="crd" comment="final_crd-j"]
20 -> 0 [label="final_val" type="val" comment="final-val"]
}
131 changes: 131 additions & 0 deletions sam.egg-info/PKG-INFO
Original file line number Diff line number Diff line change
@@ -0,0 +1,131 @@
Metadata-Version: 2.1
Name: sam
Version: 0.0.1
Summary: Sparse Abstract Machine
Home-page: https://github.com/weiya711/sam
Author: Olivia Hsu
Author-email: [email protected]
License: UNKNOWN
Description: # The Sparse Abstract Machine (SAM) IR, Compiler, and Simulator

![Master Makefile CI](https://github.com/weiya711/sam/actions/workflows/makefile.yml/badge.svg?branch=master)
![Master Python CI](https://github.com/weiya711/sam/actions/workflows/python-package-conda.yml/badge.svg?branch=master)

## SAM Front-end Compiler

Overview:
tensor expression + format language + schedule
-->
SAM Graph
-->
dot file and png of dot file
-->
RTL Graph or Simulator Graph

### Compiling SAM graphs
Init the taco/ repo as a submodule
```
make submodules
```

Setup the compilation for the taco/ repo
```
make taco/build
```

Run the script to generate a handful of example sam graphs
```
make sam
```

The example sam graphs should now be located in `compiler/sam-outputs/` in both the `dot/` and `png/` folers.

### Naming convention
Naming rules
- all (block) types are lower case: repeat, repeat_gen, fiber_lookup, fiber_write, reduce, intersect, union, sparse_accum
- network signal types are: crd, ref, val, repsig, and bv
- Tensor casing: Matrices and higher order tensors are upper case, scalars and vectors are lower case
- Index variables are going to be i, j, k, ..., etc.
- Tensor ranks are going to correspond to 0, 1, 2, ..., etc. (no longer using rows and columns)
- For a given expression result is always 'x' (or 'X') and the inputs start from 'b, c, ..., etc.' of equivalently 'B, C, ..., etc.'

Metadata Naming
Metadata naming convention for other blocks: <block name>-<metadata>
Metadata naming convention for fiber (lookup and write) blocks: fiber_<lookup|write>-<tensor>_<index>_<format>_<glb?>
Examples:
1. fiber_lookup_Bi_B0_compressed
2. repeat_Ci

## SAM Simulator
### Installing SAM Simulator as a Package
```
pip install -e .
```

### Running Tests
The simulator uses pytest to run tests

To run all tests type
```
cd sam/sim/
pytest
```

Use the following pytest optional arguments below
```
--debug-sim Turn on debug mode for sim
--count=<n> Repeat each test for n iterations
-k <testname>[<paramlist>] Run only tests with testname and paramlist
-vv Double verbose
-s Forward printouts to stdout
--full-trace Print full trace to stdout
```


### Test Naming Convention
Full kernel tests follow the naming convention `test_<kernel>_<rand|direct>_<outformat>_<in1format>_<in2format>_...<innformat>` where:
1. `<kernel>` is the name of the tensor algebra kernel being tested (e.g. mat_elemmul, mat_mul, vec_elemmul, etc.)
2. `*format` takes on `u | c | s` for formats uncompressed, compressed, singleton respectively
3. `<rand|direct> specifies if the test is _randomly generated_ or a _directed (handwritten)_ test

Primitive unit tests follow the naming convention `test_<primitive>_<feature>_<order>` where:
1. `<primitive>` is the name of the primitive being tested (e.g. array, intersect, union, etc.)
2. `<feature>` is the name of the feature being tested (e.g. for an array we can test both loads and stores)
3. `<order>` is the name of the order of stream being tested (1d for vectors,
2d for matrices, ..., and nd for all dimensions/tensor orders, etc.)


### Directory Structure
```
sim
└───src
│ │ base.py
│ │ joiner.py
│ │ ... # All primitive block classes
└───test
│ │ test.py
│ │ file022.txt
│ │
│ └───apps
│ │ test_mat_elemmul.py
│ │ ... # Full kernel/expression tests
└───────primitives
│ test_joiner.py
│ ... # Primitive unit tests

```

## SAM Binding to Onyx
See the `README` in `sam/sam/onyx`

## License
All files in this project (code, scripts, documentaiton) are released under the [MIT License](LICENSE)

Platform: UNKNOWN
Requires-Python: >=3.5
Description-Content-Type: text/markdown
21 changes: 16 additions & 5 deletions sam/onyx/hw_nodes/read_scanner_node.py
Original file line number Diff line number Diff line change
Expand Up @@ -169,6 +169,9 @@ def connect(self, other, edge, kwargs=None):

if 'use_alt_out_port' in edge_attr:
out_conn = 'block_rd_out'
elif ('vector_reduce_mode' in edge_attr):
if (edge_attr['vector_reduce_mode']):
out_conn = 'pos_out'
else:
out_conn = 'coord_out'

Expand Down Expand Up @@ -216,11 +219,19 @@ def connect(self, other, edge, kwargs=None):
raise NotImplementedError(f'Cannot connect ReadScannerNode to {other_type}')
elif other_type == RepSigGenNode:
rsg = other.get_name()
new_conns = {
f'rd_scan_to_rsg': [
([(rd_scan, "coord_out"), (rsg, f"base_data_in")], 17),
]
}
edge_attr = edge.get_attributes()
if 'vr_special' in edge_attr:
new_conns = {
f'rd_scan_to_rsg': [
([(rd_scan, "pos_out"), (rsg, f"base_data_in")], 17),
]
}
else:
new_conns = {
f'rd_scan_to_rsg': [
([(rd_scan, "coord_out"), (rsg, f"base_data_in")], 17),
]
}
return new_conns
elif other_type == CrdHoldNode:
crdhold = other.get_name()
Expand Down
6 changes: 3 additions & 3 deletions sam/onyx/parse_dot.py
Original file line number Diff line number Diff line change
Expand Up @@ -356,22 +356,22 @@ def rewrite_VectorReducer(self):

print(crd_edge_attr)
print(val_edge_attr)
del crd_edge_attr['comment']

# crd_rd_scan_to_glb = pydot.Edge(src=crd_rd_scanner, dst=dst_crd, **crd_edge_attr, use_alt_out_port="1")
# val_rd_scan_to_glb = pydot.Edge(src=vals_rd_scanner, dst=dst_vals, **val_edge_attr, use_alt_out_port="1")

# CRDDROP SUPPORT: TOOK OUT COMMENT ATTRIBUTE FROM BOTH OF THESE
crd_rd_scan_to_ds = pydot.Edge(
src=crd_rd_scanner,
dst=dst_crd,
**crd_edge_attr,
comment="final-crd",
# comment="final-crd",
vector_reduce_mode=True)
val_rd_scan_to_ds = pydot.Edge(
src=vals_rd_scanner,
dst=dst_vals,
**val_edge_attr,
comment="final-val",
# comment="final-val",
vector_reduce_mode=True)

# self.graph.add_edge(input_to_rsg_edge)
Expand Down

0 comments on commit a8cd9a8

Please sign in to comment.