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ath79: rename and sort patches by OpenWrt naming rules
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The patches in the ath79 target have not been sorted for a long time
and they are very chaotic now. This patch sorts them again according
to the OpenWrt naming rules[1], so that we can better manage them.

[1] https://openwrt.org/docs/guide-developer/toolchain/use-patches-with-buildsystem#naming_patches

Signed-off-by: Shiji Yang <[email protected]>
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DragonBluep authored and blocktrron committed Sep 8, 2023
1 parent 496280e commit c60dd7b
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Showing 35 changed files with 7 additions and 7 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@ Signed-off-by: Wenli Looi <[email protected]>
chip = "9343";
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -867,6 +867,7 @@
@@ -862,6 +862,7 @@
#define REV_ID_MAJOR_QCA9558 0x1130
#define REV_ID_MAJOR_TP9343 0x0150
#define REV_ID_MAJOR_QCA956X 0x1150
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Expand Up @@ -16,15 +16,15 @@ Signed-off-by: David Bauer <[email protected]>

--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -391,6 +391,7 @@
@@ -390,6 +390,7 @@
#define QCA955X_PLL_CPU_CONFIG_REG 0x00
#define QCA955X_PLL_DDR_CONFIG_REG 0x04
#define QCA955X_PLL_CLK_CTRL_REG 0x08
+#define QCA955X_PLL_PCIE_CONFIG_REG 0x0c
#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28
#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
#define QCA955X_PLL_ETH_SGMII_SERDES_REG 0x4c
@@ -476,6 +477,9 @@
@@ -475,6 +476,9 @@
#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21)
#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)

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Expand Up @@ -7,7 +7,7 @@ Subject: [PATCH] ath79: gmac: add parsers for rxd(v)- and tx(d|en)-delay for

--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -1226,6 +1226,10 @@
@@ -1231,6 +1231,10 @@
#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
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Expand Up @@ -16,7 +16,7 @@ Signed-off-by: David Bauer <[email protected]>

--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -1246,7 +1246,12 @@
@@ -1251,7 +1251,12 @@
*/

#define QCA955X_GMAC_REG_ETH_CFG 0x00
Expand All @@ -29,7 +29,7 @@ Signed-off-by: David Bauer <[email protected]>

#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
#define QCA955X_ETH_CFG_MII_GE0 BIT(1)
@@ -1268,9 +1273,58 @@
@@ -1273,9 +1278,58 @@
#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20

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Expand Up @@ -21,7 +21,7 @@ Submitted-by: David Bauer <[email protected]>

--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -1376,5 +1376,6 @@
@@ -1380,5 +1380,6 @@

#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0
#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7
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