sunxi: add support for H616 SoC and Orangepi Zero 2

Specifications:

SoC:     Allwinner H616 @ 1.5 Ghz
DRAM:    1Gb LPDDR3
Power:   5V USB-C
Video:   HDMI (Type 2.0A - micro)
Network: 10/100/1000Mbps Ethernet (Realtek RTL8211F), AW859A BT+wifi
Storage: microSD / 2Mb SPI flash
USB:     1 USB2.0 Host
Debug    Serial UART

Flashing instructions:
  Standard sunxi SD card installation procedure - copy image to SD card,
  insert into SD card slot on the device and boot.

Signed-off-by: Zoltan HERPAI <[email protected]>

package/boot/arm-trusted-firmware-sunxi/Makefile

@@ -36,9 +36,15 @@ define Trusted-Firmware-A/sunxi-h6
 	PLAT:=sun50i_h6
 endef
 
+define Trusted-Firmware-A/sunxi-h616
+	NAME:=Allwinner H616
+	PLAT:=sun50i_h616
+endef
+
 TFA_TARGETS:= \
 	sunxi-a64 \
-	sunxi-h6
+	sunxi-h6 \
+	sunxi-h616
 
 define Package/trusted-firmware-a/install
 	$(INSTALL_DIR) $(STAGING_DIR_IMAGE)

package/boot/uboot-sunxi/Makefile

@@ -328,6 +328,15 @@ define U-Boot/orangepi_pc2
   ATF:=a64
 endef
 
+define U-Boot/orangepi_zero2
+  BUILD_SUBTARGET:=cortexa53
+  NAME:=Xunlong Orange Pi Zero2
+  BUILD_DEVICES:=xunlong_orangepi-zero2
+  DEPENDS:=+PACKAGE_u-boot-orangepi_zero2:trusted-firmware-a-sunxi-h616
+  UENV:=h616
+  ATF:=h616
+endef
+
 define U-Boot/Bananapi_M2_Ultra
   BUILD_SUBTARGET:=cortexa7
   NAME:=Bananapi M2 Ultra
@@ -382,6 +391,7 @@ UBOOT_TARGETS := \
 	orangepi_plus \
 	orangepi_2 \
 	orangepi_pc2 \
+	orangepi_zero2 \
 	pangolin \
 	pine64_plus \
 	Sinovoip_BPI_M3 \

package/boot/uboot-sunxi/uEnv-h616.txt

@@ -0,0 +1,7 @@
+setenv mmc_rootpart 2
+part uuid mmc ${mmc_bootdev}:${mmc_rootpart} uuid
+setenv loadkernel fatload mmc \$mmc_bootdev \$kernel_addr_r uImage
+setenv loaddtb fatload mmc \$mmc_bootdev \$fdt_addr_r dtb
+setenv bootargs console=ttyS0,115200 earlyprintk root=PARTUUID=${uuid} rootwait
+setenv uenvcmd run loadkernel \&\& run loaddtb \&\& booti \$kernel_addr_r - \$fdt_addr_r
+run uenvcmd

target/linux/sunxi/cortexa53/config-6.1

@@ -66,6 +66,8 @@ CONFIG_PINCTRL_SUN50I_A64_R=y
 CONFIG_PINCTRL_SUN50I_H5=y
 CONFIG_PINCTRL_SUN50I_H6=y
 CONFIG_PINCTRL_SUN50I_H6_R=y
+CONFIG_PINCTRL_SUN50I_H616=y
+CONFIG_PINCTRL_SUN50I_H616_R=y
 # CONFIG_PREEMPT_DYNAMIC is not set
 CONFIG_QUEUED_RWLOCKS=y
 CONFIG_QUEUED_SPINLOCKS=y
@@ -83,7 +85,7 @@ CONFIG_SUN50I_A100_R_CCU=y
 CONFIG_SUN50I_A64_CCU=y
 CONFIG_SUN50I_DE2_BUS=y
 CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
-# CONFIG_SUN50I_H616_CCU is not set
+CONFIG_SUN50I_H616_CCU=y
 CONFIG_SUN50I_H6_CCU=y
 CONFIG_SUN50I_H6_R_CCU=y
 # CONFIG_SUN6I_RTC_CCU is not set

target/linux/sunxi/image/cortexa53.mk

@@ -24,6 +24,11 @@ define Device/sun50i-h6
   $(Device/sun50i)
 endef
 
+define Device/sun50i-h616
+  SOC := sun50i-h616
+  $(Device/sun50i)
+endef
+
 define Device/friendlyarm_nanopi-neo-plus2
   DEVICE_VENDOR := FriendlyARM
   DEVICE_MODEL := NanoPi NEO Plus2
@@ -108,6 +113,13 @@ define Device/xunlong_orangepi-pc2
 endef
 TARGET_DEVICES += xunlong_orangepi-pc2
 
+define Device/xunlong_orangepi-zero2
+  DEVICE_VENDOR := Xunlong
+  DEVICE_MODEL := Orange Pi Zero 2
+  $(Device/sun50i-h616)
+endef
+TARGET_DEVICES += xunlong_orangepi-zero2
+
 define Device/xunlong_orangepi-zero-plus
   DEVICE_VENDOR := Xunlong
   DEVICE_MODEL := Orange Pi Zero Plus

target/linux/sunxi/patches-6.1/460-dt-bindings-usb-Add-H616-compatible-string.patch

@@ -0,0 +1,43 @@
+From e4045c8125d88a9eb8b4f8f74b5c7955d5d9adc0 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <[email protected]>
+Date: Thu, 17 Jun 2021 10:54:22 +0100
+Subject: [PATCH 5000/5006] dt-bindings: usb: Add H616 compatible string
+
+The Allwinner H616 contains four fully OHCI/EHCI compatible USB host
+controllers, so just add their compatible strings to the list of
+generic OHCI/EHCI controllers.
+
+Signed-off-by: Andre Przywara <[email protected]>
+Acked-by: Krzysztof Kozlowski <[email protected]>
+---
+ Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 +
+ Documentation/devicetree/bindings/usb/generic-ohci.yaml | 1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
+index c5f629c5bc61..994818cb6044 100644
+--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
++++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
+@@ -30,6 +30,7 @@ properties:
+               - allwinner,sun4i-a10-ehci
+               - allwinner,sun50i-a64-ehci
+               - allwinner,sun50i-h6-ehci
++              - allwinner,sun50i-h616-ehci
+               - allwinner,sun5i-a13-ehci
+               - allwinner,sun6i-a31-ehci
+               - allwinner,sun7i-a20-ehci
+diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
+index f838f78d6164..4fcbd0add49d 100644
+--- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
++++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
+@@ -20,6 +20,7 @@ properties:
+               - allwinner,sun4i-a10-ohci
+               - allwinner,sun50i-a64-ohci
+               - allwinner,sun50i-h6-ohci
++              - allwinner,sun50i-h616-ohci
+               - allwinner,sun5i-a13-ohci
+               - allwinner,sun6i-a31-ohci
+               - allwinner,sun7i-a20-ohci
+-- 
+2.20.1
+

target/linux/sunxi/patches-6.1/461-dt-bindings-phy-Add-special-clock-for-Allwinner-H616.patch

@@ -0,0 +1,82 @@
+From e2078ae0c559b6ac91db19262b56d8cf334354cb Mon Sep 17 00:00:00 2001
+From: Andre Przywara <[email protected]>
+Date: Mon, 12 Sep 2022 00:03:22 +0100
+Subject: [PATCH 5001/5006] dt-bindings: phy: Add special clock for Allwinner
+ H616 PHY
+
+The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves
+some resources from port 2's PHY and HCI IP. In particular the PMU clock
+for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL
+register of port 2. To allow each USB port to be controlled
+independently of port 2, we need a handle to that particular PMU clock
+in the *PHY* node, as the HCI and PHY part might be handled by separate
+drivers.
+
+Add that clock to the requirements of the H616 PHY binding, so that a
+PHY driver can apply the quirk in isolation, without requiring help from
+port 2's HCI driver.
+
+Signed-off-by: Andre Przywara <[email protected]>
+---
+ .../phy/allwinner,sun8i-h3-usb-phy.yaml       | 26 +++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
+index 77539b4601c2..2df012d13655 100644
+--- a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
++++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
+@@ -36,18 +36,22 @@ properties:
+       - const: pmu3
+
+   clocks:
++    minItems: 4
+     items:
+       - description: USB OTG PHY bus clock
+       - description: USB Host 0 PHY bus clock
+       - description: USB Host 1 PHY bus clock
+       - description: USB Host 2 PHY bus clock
++      - description: PMU clock for host port 2
+
+   clock-names:
++    minItems: 4
+     items:
+       - const: usb0_phy
+       - const: usb1_phy
+       - const: usb2_phy
+       - const: usb3_phy
++      - const: pmu2_clk
+
+   resets:
+     items:
+@@ -96,6 +100,28 @@ required:
+   - resets
+   - reset-names
+
++allOf:
++  - if:
++      properties:
++        compatible:
++          contains:
++            enum:
++              - allwinner,sun50i-h616-usb-phy
++    then:
++      properties:
++        clocks:
++          minItems: 5
++
++        clock-names:
++          minItems: 5
++    else:
++      properties:
++        clocks:
++          maxItems: 4
++
++        clock-names:
++          maxItems: 4
++
+ additionalProperties: false
+
+ examples:
+-- 
+2.20.1
+