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Merge master to openfpga feature branch #2572

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Merge master to openfpga feature branch #2572

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Tulong4Dev
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Merge master to openfpga feature branch.
There are test failures which look like to be caused by RSA settings.

amin1377 and others added 30 commits March 27, 2024 14:46
@amin1377
vpr: only pass rr_graph view and node id to is_inter_cluster_node
368d588
@amin1377
vpr: remove unused variables
363c70a
@amin1377
make format
65c4c3d
@amin1377
vpr: graphic: edge is not valid for drawing if one of its endpoints i…
86df937 
…s an intra-cluster pin
@amin1377
vpr: graphics: don't draw pin or sink/source if they are inside a clu…
ae854f5 
…ster
@amin1377
vpr: graphic: do not draw a partial route if it is inside a cluster
269790e
@w0lek
remove timing report modification, adding report metadata string to t…
ec044ec 
…he end of the report (will be used in parser on client side)
@w0lek
minimize diff in tatum/TimingReporter.cpp
d7e28d4
@w0lek
fix spellmistake, rename from OPTION_IS_FLOAT_ROUTING to OPTION_IS_FL…
f941c6a 
…AT_ROUTING
@w0lek
correct spell mistake, renaming OPTION_HIGHTLIGHT_MODE to OPTION_HIGH…
b0fbefd 
…LIGHT_MODE
@w0lek
move gtkcomboboxhelper into draw subfolder
8dfc1ae
@w0lek
spell correction
94aaf71
@w0lek
typo in comment
df14178
@w0lek
few minor fixes
94ddbba
@w0lek
typo in comment
c871dd5
@w0lek
few more minor fixes in telegramoptions.h
927bc3a
@w0lek
typo in var name fix
9f636d6
@w0lek
few more minor fixes
5002740
@w0lek
add default constructor for TelegramBuffer, requested in PR
8bb4a9d
@w0lek
using stream.eof() in tryConvertToInt
51525cf
@w0lek
constructor TelegramBuffer(int) is explicit
6f6c7fd
@w0lek
TelegramOptions::isDataTypeSupported is const
ff4be46
@amin1377
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
b456298 
…rilog-to-routing into pres_fac_max
@w0lek
tryConvertToInt uses vtr::atoi
d3c5180
@w0lek
gtkcomboboxhelper.cpp and .h, update documentation, replace anonymous…
6cab9c4 
… namespace with static function
@w0lek
GateIO add deletion constructors
62cc12a
@w0lek
add doc for public methods of gateio, improve GateIO::takeReceivedTas…
07d4fa3 
…ks and GateIO::moveTasksToSendQueue
@w0lek
add comment to gateio.h about tasksMutex
b5d3994
@w0lek
GateIO information about usage from main thread is added
ab867d3
@w0lek
move TelegramOptions definitions to a .cpp file
bed8f4b
AlexandreSinger and others added 19 commits May 27, 2024 12:30
@AlexandreSinger
[Warnings] Removed Deprecated STD Iterator From Timing Tags
63d57e7
@vaughnbetz
Merge pull request #2559 from verilog-to-routing/s10_fix_comments
6cbf119 
Fix the S10 arch file comments for routing segments and switches
@vaughnbetz
Merge pull request #2561 from AlexandreSinger/feature-remove-std-iter…
f523a0f 
…ator

Removed Less-Simple Uses of STD Iterator
@soheilshahrouz
add comments
3df3b6b
@amin1377
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
43b2c4a 
…rilog-to-routing into pres_fac_max
@amin1377
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
1bc8d77 
…rilog-to-routing into fix_3d_delay
@AlexandreSinger
[Docs] Updated Subtree Docs
a94b9bf 
The documentation on subtrees was a bit out of date. The command to
update a subtree now requires a message.

Added a section on how to push changes from VTR back into the upstream
subtree repo.

Added a tutorial on how to synchronize libtatum with the Tatum repo.
@amin1377
[test] update nightly_test_1 golden result
27839bd
@amin1377
[vpr][router] fix fuction signiture
7bea33f
@vaughnbetz
Merge pull request #2567 from AlexandreSinger/feature-update-subtree-…
817a956 
…docs

[Docs] Updated Subtree Docs
@amin1377
fix a typo
313eb02
@amin1377
Merge branch 'master' into fix_3d_delay
bb4073c
@amin1377
Merge branch 'master' into pres_fac_max
24d69c0
@vaughnbetz
Merge pull request #2563 from verilog-to-routing/temp_cleanup_
9343ee9 
Minor router lookahed cleanup
@vaughnbetz
Merge pull request #2514 from ThomasJagielski/bug-fix-asymmetric-grid…
7ed749f 
…-bidirectional-routing

Bug fix: asymmetric grid with bidirectional routing
@amin1377
Merge pull request #2490 from verilog-to-routing/fix_3d_delay
486be09 
Fix 3D SIV Delay & Median Move
@vaughnbetz
Merge pull request #2523 from verilog-to-routing/pres_fac_max
efe7cc0 
Set the maximum pres_fac
@Tulong4Dev
Merge branch 'master' of github.com:verilog-to-routing/vtr-verilog-to…
8c62b8c 
…-routing into openfpga
@Tulong4Dev
add missing change.
287b569
@Tulong4Dev Tulong4Dev requested a review from tangxifan May 30, 2024 22:21
@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool libarchfpga Library for handling FPGA Architecture descriptions docs Documentation lang-cpp C/C++ code infra Project Infrastructure build Build system lang-make CMake/Make code libvtrutil external_libs labels May 30, 2024
@AlexandreSinger
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AlexandreSinger commented May 31, 2024 •
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@Tulong4Dev The test failures you are seeing are likely caused by a recent change in VTR master which made the CI fail on warning for those tests. If your branch has warnings, it will fail those tests. See PR #2555 which introduced this change.

Since you are not merging into master, and if you would prefer to keep the warnings, you can opt to remove -DCMAKE_COMPILE_WARNING_AS_ERROR=on from these tests in .github/workflows/test.yml. It will run the CI as normal, but will allow warnings to pass through. You can also resolve the warnings and make the openfpga branch warning clean.

On master we opted to fail on warning to prevent mistakes and deprecations in the master branch of VTR.

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@tangxifan tangxifan Awaiting requested review from tangxifan

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build Build system docs Documentation external_libs infra Project Infrastructure lang-cpp C/C++ code lang-make CMake/Make code libarchfpga Library for handling FPGA Architecture descriptions libvtrutil VPR VPR FPGA Placement & Routing Tool
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8 participants
@Tulong4Dev @AlexandreSinger @amin1377 @w0lek @vaughnbetz @soheilshahrouz @MohamedElgammal @kimiatkh