Added the option to load external clustering attraction data #2376
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Add assertion for external atrraction data load
vaughnbetz
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Sep 12, 2023
f7a8284c7b Release version 0.30
73badeccef Bump version
8cb3bab479 Merge pull request #3792 from pu-cc/gatemate-bram-updates
61387d78b7 gatemate: Prevent implicit declaration of `ram_{we,en}`
62fc118548 Merge pull request #3790 from zeldin/makefile-posix-test
7c606bd5a3 Merge pull request #3791 from nakengelhardt/nak/show_attr_wires
6f5d984bdb Merge pull request #3778 from jix/yw_clk2fflogic
88c849d112 Bump version
d7f25165a5 Add ninitff line to aiger .aim files
0707b911c7 show: add -viewer none option
4b986c9c65 fix wire color after BUF
2004a9ff4a gatemate: Add CC_FIFO_40K simulation model
c244a7161b gatemate: Fix SDP read behavior
43b807fe6f Bump version
1cd1e57e3c Fix use of non-POSIX test expressions in Makefile
fb7af093a8 intel_alm: re-enable 8x40-bit M10K support
26555a998d show -colorattr: extend colors to arrows when wires have attribute
8596c5ce49 Bump version
cac1bc6fbe intel_alm: enable M10K initialisation
ec8d7b1c68 abc9_ops -prep_hier to unmap entire module
862631d657 Add ABC9 DSP cascade test
00b0e850db intel_alm: re-enable carry chains for ABC9
e36c71b5b7 Use clk2fflogic attr on cells to track original FF names in witnesses
7caeb922a0 sim: Run level triggered async updates to fixpoint during initialization
52c8c28d2c Add recover_names pass to recover names post-mapping
57c9eb70fe Bump version
5e36effe3c Merge pull request #3777 from YosysHQ/micko/vhdl_verific
ecd289c100 Fix importing parametrized VHDL entity
4f3d1be96a Merge pull request #3767 from YosysHQ/krys/yw_fix
5fb1223861 Merge pull request #3733 from AdamHillier/aiger-inputs
890849447f Merge pull request #3716 from antmicro/kr/brackets
cdeef5481c Bump version
e7156c644d Standard compliance for tests/verilog/block_labels.ys
ad2b04d63a sim: Fix cosimulation with nested modules having unconnected inputs
e6f3914800 smt2: Use smt bv offset for `$any*`'s smtoffset
147cceb516 Bump version
52ad7a47f3 Assign wires an smtoffset
c2285b3460 fix file rights
07e76fcaca Merge pull request #3751 from RTLWorks/main/issue2525
693c609eec Merge branch 'YosysHQ:master' into main/issue2525
665e0f6131 remove new line per maintainer request
acfdc5cc42 Merge pull request #3755 from RTLWorks/muthu/issue3498
6b3e6d96a3 Fix missing brackets around else
d82bae32be Bump version
c855502bd5 Update passes/techmap/libparse.cc
7aab324e85 Merge pull request #3737 from yrabbit/all-primitives-script
5c7cc6ff06 Merge pull request #3745 from rfuest/gowin_alu
226a224640 Merge pull request #3749 from lethalbit/aki/plugin-stuff
f790e00478 Next dev cycle
9c5a60eb20 Release version 0.29
0469405abf Bump version
266036c6f9 Merge pull request #3756 from YosysHQ/krys/sim_writeback
0aeb6105eb Merge pull request #3736 from jix/conc_assertion_in_unclocked_proc_ctx
ec56e625f4 Merge pull request #3742 from jix/fix_rename_witness_cell_renames
5a4e72f57a Fix sim writeback check for yw_cosim
17cfc969dd [YOSYS] Issue #3498 - Fix Synopsys style unquoted Liberty style function body parsing with unittest
8341fd450e Merge branch 'master' into all-primitives-script
4251d37f4f Merge pull request #3610 from YosysHQ/synthprop
d2f3251528 adding unittest
81e089cb60 [YOSYS-2525] fix read_liberty newline handling #2525 - newlines can be allowed in function parsing
4f6a66e257 Merge branch 'master' into all-primitives-script
f93671eb85 Bump version
32f5fca2aa Merge pull request #3694 from daglem/struct-attributes
fb7f3bb290 Cleaner tests for RTLIL cells in struct_dynamic_range.sv
ad437c178d Handling of attributes for struct / union variables
bb240665b7 plugin: shuffled the `#ifdef WITH_PYTHON`'s around to un-tangle the code and pulled out the check for the `.py` extension so it will complain if you try to load a python extension without python support
572c8df9a8 plugin: Re-vamped how plugin lookup was done to make it more consistent with the rest of yosys, and prevented a case where you could end up with `.so.so` on the end
30f1d10948 gowin: Fix X output of $alu techmap
2bab787729 Merge branch 'master' into all-primitives-script
7bff8b63b3 rename: Fix renaming cells in -witness mode
cee3cb31b9 Merge pull request #3734 from jix/fix_unbased_unsized_const
51dd029024 Bump version
8611429237 ABC9: Cell Port Bug Patch (#3670)
a1dd794ff8 gowin: Add all the primitives.
3cbca5064c verific: Handle non-seq properties with VerificClocking conditions
ec47bf1745 verific: Handle conditions when using sva_at_only in VerificClocking
985f4926b7 verilog: Fix const eval of unbased unsized constants
3861cc31f0 Add outputs before inputs to the sigmap in the AIGER backend.
7efc50367e Bump version
88ae463ffe Merge pull request #3732 from hzeller/20230417-remote-statement-no-effect
a3a8f7be38 Remove a statement without effect.
a9c792dcee Bump version
d0855576ae Next dev cycle
0d6f4b0683 Release version 0.28
b377a39b73 Merge pull request #3727 from YosysHQ/micko/pll_bram
a2655a4b70 Bump version
e56dad56c4 fabulous: Add support for LUT6s
f9a6c0fcbd gowin: Add serialization/deserialization primitives
ee3162c58d Add PLL and EBR related primitives
101075611f Bump version
266f81816b ecp5: Remove TRELLIS_SLICE and add TRELLIS_COMB model
0f5e7c244d add additional dff and lutram tests
54d313efc3 add test for CCU2D
9e9fae1966 Add more DFF types
d5a405d3b4 Added proper simulation model for CCU2D
6e4c1675e7 Generate TRELLIS_DPR16X4 for lutram
6e12da3956 machxo2: Initial support for carry chains (CCU2D)
53c0a6b780 Bump version
f35bdaa527 Update Xilinx cell definitions, fixes #3699
23826e5152 Bump version
dc0a799c06 Merge pull request #3708 from jix/void_func
fb1c2be76b verilog: Support void functions
61da330a38 Update tests
ff9f1fb86e Start unification effort for machxo2 and ecp5
4d7e9e2e5d Add additional iopad_external_pin attributes
db367bd69e Add iopad_external_pin to some basic io primitives
10589c57bf insert IO buffers for ECP5, off by default
ceef00c35e Bump version
57fb1f51b2 Merge pull request #3704 from jix/enum_values
390d1c583a verific: Fix enum_values support and signed attribute values
101d19bb6a Bump version
c50f641812 Merge pull request #3682 from daglem/struct-member-out-of-bounds
baa3659ea5 ice40: Fix path delay definitions
1af7d6121f Added test for dynamic indexing within struct members
b58664d441 Bump version
7c5ae560a8 Merge pull request #3684 from YosysHQ/fix-GIT_REV
368f2984cd Next dev cycle
5f88c218b5 Release version 0.27
0d3423ddea Index struct/union members within corresponding wire chunks
9747e55d95 Bump version
3f173c2180 Makefile: fix GIT_REV extraction if Yosys is built as submodule.
981c934b5b Merge pull request #3690 from whitequark/smtbmc-help-opt
25ebefc2a6 Merge pull request #3692 from nakengelhardt/stat_q_fix
1a3ff0d926 Merge pull request #3688 from pu-cc/gatemate-reginit
57897927ff stat: pass down quiet arg
bb28e48136 Merge pull request #3663 from uis246/master
4ff9063145 Merge pull request #3652 from martell/elvds
71c59d9fab Bump version
4bb173e256 yosys-smtbmc: support -h/--help (and exit with code 0).
21e87f7986 Merge pull request #3646 from YosysHQ/lofty/fix-3591
842cdad575 Merge pull request #3674 from YosysHQ/fix_wide_case
2ab3747cc9 fabulous: Add support for mapping carry chains
28c4aac234 run verific tests in test target
d8cefec169 Added ranged case check
53a4f0fb56 Add test example
a30894e5fa Handle more wide case selector types
8216b23fb7 Bump version
ef8ed21a2e Merge pull request #3685 from YosysHQ/update-abc
5d9bd0af92 Update abc.
0f2d226ae9 Bump version
c8966722d2 Merge pull request #3403 from KrystalDelusion/mem-tests
f80920bd9f Genericising bug1836.ys
445a801a85 bug3205.ys removed
51c2d476c2 Removing extra `default_nettype` lines
8f6a06951c Fix for sync_ram_sdp not being final module
7f033d3c1f More tests in memlib/generate.py
af1b9c9e07 Tests for ram_style = "huge"
de2f140c09 Testing TDP synth mapping
48f4e09202 Asymmetric port ram tests with Xilinx
ac5fa9a838 Addings tests for #1836 and #3205
79043cb849 Out of bounds checking for struct/union members
f0116330bc Bump version
f30b539cc2 Merge pull request #3681 from keszocze/keszocze-patch-dsp48e1-init-dreg
fc56978703 Check DREG attribute
1cfedc90ce Bump version
25e7cb3bbb fabulous: Add CLK to BRAM interface primitives
a20804c6ed Bump version
2c7ba0e752 gatemate: Enable register initialization
1c667fab2b Merge pull request #3672 from jix/yw-cosim-hierarchy-fixes
1cedad7a68 Merge pull request #3675 from daglem/struct-item-queries
68480dfa19 Merge pull request #3671 from zachjs/master
f8219289b2 Corrected tests for data and array queries on struct/union item expressions
c1e12877f0 Support for data and array queries on struct/union item expressions
53bda9de54 Merge pull request #3661 from daglem/struct-array-range-offset
59de4a0e7f Bump version
ec94703619 Merge pull request #2995 from georgerennie/cover_precond
85f611fb23 Merge pull request #3126 from georgerennie/equiv_make_assertions
b636af9751 chformal: Note about using -coverenable with the Verific frontend
f37073050b gatemate: Update CC_PLL parameters
6a7d5257cd gatemate: Add CC_USR_RSTN primitive
4cb27b1a3a gatemate: Ensure compatibility of LVDS ports with VHDL
e0bc25f1af Bump version
d2032ac6fd Merge pull request #3669 from jix/fix-xprop-tests-yosys-call
550a5b7b6b Update license
713b7d3e26 added support for latched output reset
131b557727 Initial implementation of synthesizable assertions
55ad3fe6c7 xprop tests: Make iverilog invocation more portable
2a68eee5f1 xprop: Test fixes and abort on test failure
9f20beb7df xprop: Smaller subset of tests to run by default
160eeab2bb verilog_backend: Do not run bwmuxmap even if in expr mode
1698202ccc sim: For yw cosim, drive parent module's signals for input ports
4c334b905f Bump version
615adc4253 Resolve package types in interfaces (#3658)
26a6c60478 Add test for typenames using constants shadowed later on
5ea2c290a5 Bump version
6d021f04d4 tests: Fix path of yosys invocation in xprop tests
f3c4e93d24 Merge pull request #3667 from jix/xprop-test-make-fix
d31d5da69f tests: in xprop tests, use MAKE variable if set
b1a011138c Bump version
a7099b0a72 Next dev cycle
7e588664e7 Release version 0.26
ddb2bd85c8 Merge pull request #3662 from YosysHQ/micko/wide_case_select_box
5f33c0e0b2 Updated changelog
109b88c379 For case select values use Sa instead of Sx and Sz
ea6f562d49 gowin: Add new types of oscillator
417fadbefd Merge pull request #3625 from povik/show_cleanup
e7e37df91b Add verific import support for OPER_WIDE_CASE_SELECT_BOX
777c589e85 Handle range offsets in packed arrays within packed structs
45edc8eb98 Bump version
5fa96ccdee Merge pull request #3659 from whitequark/update-abc
3af3cc15b5 Bump ABCREV to fix WASM build.
54bf15a5b8 Bump version
a90f940615 backends/firrtl: Ensure `modInstance` is valid
221036c5b6 Bump version
0f2cb80a26 Merge pull request #3655 from jix/smt2_fix_b_op_width
5e82638408 smt2: Fix operation width computation for boolean producing cells
f7c1e4aadf Bump version
c235802f4a Merge pull request #3650 from jix/rtlil_roundtrip_z_bits
419f91a2b9 add option to fsm_detect to ignore self-resetting
ecfa7e9fbc add pmux option to bmuxmap for better fsm detection with verific frontend
dbc8b77222 gowin: Add support for emulated differential output
d11cb6901f Bump version
26db5a11d3 Resolve struct member package types
db13c6df2b Handle struct members of union type (#3641)
b08a880704 backends/rtlil: Do not shorten a value with z bits to 'x
822c7b0341 muxcover: do not add decode muxes with x inputs
541fdffff2 Bump version
b9155a574e Merge pull request #3647 from jix/formalff-hierarchy-fix
afac3f2c76 formalff: Fix crash with _NOT_ gates in -hierarchy mode
755b753e1a Bump version
8180cc4325 Merge pull request #3624 from jix/sim_yw
245884a101 Merge pull request #3629 from YosysHQ/micko/clang_fixes
9bc9121b9e Merge pull request #3636 from YosysHQ/log_plugin
bfacaddca8 show: Remove left-in debug log_warning
200ffdccc5 Call yosys_shutdown to properly cleanup plugins and tcl when expecting error
611f71c670 Merge pull request #3630 from yrabbit/gw1n4c-pll
29e7756b0c Bump version
bfc3c20cfb Improve splitcells pass
6574553189 Fixes for some of clang scan-build detected issues
f9e30ee5e0 passes: show: s/pos/bitpos/ for readability
314b864205 passes: show: Reuse string parts in generation of portboxes
61abca10a3 passes: show: Touch chunk iteration in gen_portbox
60318a5cd8 passes: show: Label no_signode flag
8b1f5fba62 passes: show: Simplify wire bit range logic
ad149cc42a passes: show: Factor out 'join_label_pieces'
5848790835 passes: show: Label signed_suffix flag
13700e12e5 passes: show: s/idx/dot_idx/ for readability
e3709ce776 passes: show: Fix portbox bit ranges in case of driven signals
956c4e485a Bump version
692a0fa33b print filename in liberty log_header
d6c7aa0e3d sim/formalff: Clock handling for yw cosim
7ddec5093f sim: Improvements and fixes for yw cosim
636b9f2705 Support for BTOR witness to Yosys witness conversion
3e25e61778 aiger: Use new JSON code for writing aiger witness map files
29461ade17 Add json.{h,cc} for pretty printing JSON
dda972a148 sim: New -append option for Yosys witness cosim
2dd5652215 sim: Add Yosys witness (.yw) cosimulation
1494cfff00 New kernel/yw.{h,cc} to support reading Yosys witness files
f6458bab70 sim: Only check formal cells during gclk simulation updates
9c6198a827 sim: Internal API to set $initstate
44b26d5c6d sim: Emit used memory addresses as signals to output traces
5042600c0d xprop, setundef: Mark xprop decoding bwmuxes, exclude them from setundef
673ad561b8 smt2: Treat bweqx as xnor
62afe61779 smt2: Directly implement bwmux instead of using bwmuxmap
4173daa708 Merge pull request #3605 from gadfort/stat-json-area
2e3c08adc4 Merge pull request #3570 from YosysHQ/claire/eqystuff
843f329b96 Merge branch 'master' into claire/eqystuff
5abaa59080 Merge pull request #3537 from jix/xprop
d742d063d4 remove template declaration that stops function from being used
41ce00e82a Merge pull request #3620 from YosysHQ/gcc48_remove
4fc5207b1e Add deprecation info to changelog
5801152779 Deprecate gcc-4.8
6d56d4ecfc Merge branch 'master' of github.com:YosysHQ/yosys into claire/eqystuff
d6a1e022e1 gowin: add a new type of PLL - PLLVR
7b476996df Bump version
2677569d48 Merge pull request #3616 from YosysHQ/register_error
2b622258a2 Merge pull request #3615 from YosysHQ/qbfsat_cvc5
40282576b0 Display error instead of assertion when pass exists
e3c0fd8b10 qbfsat support for cvc5, fixes #3608
f2c689403a Bump version
7bac1920b2 nexus: Fix BRAM write enable in PDP mode
d3216593da Bump version
c34d308bbd Next dev cycle
e02b7f64bc Release version 0.25
a27a297ebc Bump version
7971154e72 Merge branch 'master' into stat-json-area
583ab81670 Merge pull request #3606 from YosysHQ/fix_vs
a935752df6 Remove cache
fcd1c68ab7 add note to help about how to chain commands
257b41cd1f Merge pull request #3577 from KrystalDelusion/deprecate_manual
58cca9592d stat: ensure area is included in json output
029b0aac7f Merge branch 'claire/eqystuff' of github.com:YosysHQ/yosys into claire/eqystuff
1bc832a8e1 Allow non-unique modules without state in sim writeback-mode
a9072dc23c Small bugfix in uniquify pass
3ebc50dee4 Merge pull request #3467 from jix/fix_cellarray_simplify
f2a4e5f1a0 Fixing other references to the manual
f33a21eea4 Removed manual from make clean
aeb40d4ddf Remove make targets for manual
69cbef9666 Bump version
76de4455e6 Merge pull request #3588 from YosysHQ/noblackbox
b867dee241 respect noblackbox attribute in verific
5d893c4b03 Bump version
4a0ed35aab xprop: Improve signal splitting code
2093cf07e4 Merge pull request #3581 from jix/formalff-error
6a6e1d8424 Improvements in "viz" pass
967529abb1 formalff: Proper error messages on async inputs for the -clk2ff mode
dc14def5f3 Add gold-x handing to miter cross port handling
3454bddbe2 Merge branch 'claire/eqystuff' of github.com:YosysHQ/yosys into claire/eqystuff
4f36a86fff Merge pull request #3579 from jix/split_public_untested
172a8e79f0 xprop: Add -split-public option
7ad7b550cb Merge pull request #3573 from daglem/struct-array-multidimensional
cf3570abde simplify: regression test for AST_CELLARRAY simplification issue
dd8b412833 simplify: Do not recursively simplify AST_CELL within AST_CELLARRAY
11fe4d0862 Remove help outputs for tex
a955c42d6c And appnotes
1eec255e60 Removing manual files
4b95fac139 Removing old manual from README.md
068031d2aa Improvements in "viz" command
aeba966475 Improvements in "viz" pass
c679b408cb Various improvements in "viz" command
2895a66784 Bugfix in splitcells pass
1f6ac926a4 Bump version
f1da4b0204 Next dev cycle
313b7997b5 Release version 0.24
2dac9be3cd Update manual
b60baad662 Merge pull request #3572 from jix/tcl-recover
6589accfa9 tcl: Update help message to mention 'tee -s'
9362fdb4c6 Merge pull request #3568 from YosysHQ/verific_msg
26aaf7683f Merge pull request #3569 from YosysHQ/ver_no_rewriters
a43356cb04 tcl: Unset both result.json and result.string only before calling pass
e151e44caa Improvements in "viz" command
c9f4b06cb2 Add "viz" pass for visualizing big-picture data flow in larger designs
22090011ab Made make_struct_member_range side-effect-free again
92fc6cd4a9 Add splitcells pass
8895b51dbb Merge branch 'master' of github.com:YosysHQ/yosys into claire/eqystuff
f94eec952f Support for packed multidimensional arrays within packed structs
34a64aa322 set VERI-1063 explicitly
0f7b8b8d23 tcl: Don't exit repl on recoverable command errors
5524d5185d tcl: Return scratchpad result.json and result.string as tcl objects
7036a312bf stat: Fix JSON output for empty designs
ed02d52f30 tee: Allow logging command output to a given scratchpad value
a64ed824ed Merge pull request #3567 from YosysHQ/tcl_fix_crash
956b7f5fd1 Merge branch 'xprop' of github.com:jix/yosys into claire/eqystuff
fbf8bcf38f Add insbuf -chain mode
dcc1cb7ddd Bump version
4a2b7287ca Merge pull request #3551 from daglem/struct-array-swapped-range
64f88eb7f1 Added asserts for current limitation of array dimensions in packed structs
15c8e74329 Check for all cases of currently unsupported array dimensions in packed structs
eb0039848b miter: Add -make_cover option to cover each output pair difference
551ca7f97f formalff: Fix -ff2anyinit assertion error for fine FFs
ce708122a5 New xprop pass to encode 3-valued x-propagation using 2-valued logic
5ff69a0fe2 sim: Improved global clock handling
3ecf85e32c opt_expr: Optimizations for `$bweqx` and `$bwmux`
be752a20dc Add bwmuxmap pass
7203ba7bc1 Add bitwise `$bweqx` and `$bwmux` cells
f2c531e65f verilog_backend: Do not run bmuxmap or demuxmap in -noexpr mode.
82b630a246 verilog_backend: Correctly sign extend output of signed `$modfloor`
5cb7d0fe9d verilog_backend: Add -noparallelcase option
99163fb822 simlib: Use optional SIMLIB_GLOBAL_CLOCK to define a global clock signal
605d127517 simlib: Silence iverilog warning for `$lut`
39ac113402 simlib: Fix wide $bmux and avoid iverilog warnings
b982ab4f59 satgen, simlib: Consistent x-propagation for `$pmux` cells
1e67c3a3c2 opt_expr: Fix shift/shiftx optimizations
2dd55d73a0 reset elaboration error after rewriter
bfd79845b6 Set all verific messages of certain type to other
b0469b3863 Fix tcl crash in case of error executing command
fd56d1f79e opt_expr: Constant fold mux, pmux, bmux, demux, eqx, nex cells
c08242ba41 opt_expr: Optimize bitwise logic ops with one fully const input
661fa5ff92 simplemap: Map `$xnor` to `$_XNOR_` cells
f9db7c0599 Bump version
10e22608c0 Merge pull request #3565 from jix/sat-def-formal
ed0e14820e sat: Add -set-def-formal option to force defined $any* outputs
23e26ff661 Bump version
fd01d9eb8b Merge pull request #3561 from YosysHQ/tcl_shell
448a796e15 Merge pull request #3560 from YosysHQ/verific_conf
2450e6be22 Add TCL interactive shell mode
f764cd1655 update documentation
b0be19c126 Support importing verilog configurations using Verific
c55c514cdb Bump version
b9b5899cce Remove docs dependency on yosys repo (#3558)
a460e0b31c Tests for unpacked arrays in packed structs are for the Yosys frontend only
ddb12148e7 Support for swapped ranges in second array dimension
fc2f622a27 Merge pull request #3552 from daglem/fix-sv-c-array-dimensions
13e4f343b9 Bump version
239ecf9185 Merge branch 'zachjs-master'
b64141f48b mention prerequisites in fsm_detect and fsm help
e56c689962 Bump version
b6467f0801 fabulous: Allow adding extra custom prims and map rules
f111bbdf40 fabulous: improvements to the pass
e3f9ff2679 fabulous: Unify and update primitives
12c22045b7 Introduce RegFile mappings
2b07e01ea4 Replace synth call with components, reintroduce flags and correct vpr flag implementation
df56178567 Reorder operations to load in primitive library before hierarchy pass
da32f21b59 Add plib flag to specify custom primitive library path
950dde3081 Remove flattening from FABulous pass
8fdf4948a8 Remove ALL currently unused flags (some to be reintroduced later and passed through to synth)
2e9480be24 Add synth_fabulous ScriptPass
0516fd751c Bump version
48659ee2bb Slowing down clock to have same metadata
388611aac4 Bump version
7de226878d faketime to make PDFs unique
a14dec79eb Rst docs conversion (#3496)
853f4bb3c6 Merge pull request #3547 from YosysHQ/update_abc
a862642fac Correct interpretation of SystemVerilog C-style array dimensions
bab88630c2 Support for arrays with swapped ranges within structs
553eb6ac1e Bump version
c75f12a989 Add missing memory width assert preventing division by zero (#3546)
6403bfbd9f Update ABC
faa1c2e7fe Bump version
cb7299c3dc Next dev cycle
7ce5011c24 Release version 0.23
6758b7babc Update manual
2cdbb85da6 Bump version
4cb923a4f5 Merge pull request #3544 from jix/cosim-ffinit
9b4fba3870 sim: Run a comb-only update step to set past values during FST cosim
cff42f0af5 Update CHANGELOG
96df99dafa Merge pull request #3536 from YosysHQ/claire/vcdend
bc0e69f5c8 Merge pull request #3543 from jix/fstdata-fixes
68d52cb1b1 fstdata: Update past_data before end_time callback
3477f2d00b fstdata: Handle square/angle bracket replacemnt, change memory handling
9470ef9efe Update CHANGELOG
14aa485176 Bump version
310281a96c Separate deprecated compilers on CI
a4eb7e41c0 Add extra time at the end of a sat VCD trace
d8ea5ef6e2 Bump version
8d69220be7 Merge pull request #3533 from YosysHQ/micko/liberty
59b6ac47c9 Add additional help info
499390e9ce Merge pull request #3534 from mmicko/win32_plugins
6fb80bce15 Enable importing blackbox modules only
e702f2894a Support for reading liberty files using verific
d1b3a250db Windows plugin build support
5f209f8be5 Bump version
fe438ca1ab Add missing log_dump_val_worker forward declarations
c0ad6b3bc6 Bump version
71e7e09092 verilog: Support module-scoped task/function calls
31c15e5fa6 Merge pull request #3530 from jix/simlib-mux-fix
aa7e7df19f simlib: Simplify recently changed $mux model
05218ec900 Add dlfcn library for win32
518194fac1 Bump version
fdce6c5868 Merge pull request #3528 from YosysHQ/claire/crossbits
d04c17fd58 Add miter -cross option
408fc60c95 Merge pull request #3526 from jix/mux-simlib-eval
3a37597e9f Merge pull request #3518 from jix/smtmap
9f76ff0b6a Merge pull request #3517 from jix/smtbmc-witness-no-assume-skipped
61440a42d1 Merge pull request #3523 from lparkes/basename
c77b7343d0 Consistent $mux undef handling
c0e4d01aa7 Merge pull request #3512 from lparkes/fstapi
7fcc39abe3 Update CodeQL action
49945ab1c2 Replace GNU specific invocation of basename(1) with the equivalent POSIX one. The tests now complete on BSD as well as GNU/Linux.
713d42d25d Bump version
32808b26c6 Merge pull request #3521 from YosysHQ/ci_upgrade
61dfc26d74 Update versions of CI actions used
4f4cff0080 Bump version
0f96ae5990 Add smtmap.v describing the smt2 backend's behavior for undef bits
be1a12595a Add missing log_dump handler for std::vector<>
96029400cb smtbmc: Do not assume skipped assertions when loading a witness trace
6781746872 Bump version
8859d801c8 Temporal induction counterexample loop detection (#3504)
f4ede15d68 Merge pull request #3514 from jix/smtbmc-kind-witness-fix
8838b1eaa4 smtbmc: Fix witness handling for k-induction failures
7dcc9c664e And another place we need to lseek() after dup().
635aa2a3fc Forcibly set the current seek location of gz files that we are accessing via dup(fileno());gzdopen() because stdio might have buffered data from the underlying file meaning that the underlying seek position isn't what we think it is.
d02ae8f2fc Bump version
fc53a0a5c2 Merge pull request #3511 from YosysHQ/improve_edif
48628fbf5a Skip verific primitives and operators import by default
922f8b614a Add option to import all cells from all libraries
2e837956dc Bump version
33a2773de0 Merge pull request #3510 from jix/ff_witness_fixes
4d334fd3e3 smt2/smtbmc: Fix FF witness data for fine grained or multi chunk FFs
f35c062354 github: issues: added an OS dropdown to the issue template
fcf742837e Merge pull request #3502 from jix/equiv_opt_fixes
5c7a1eda92 Bump version
00bef0b534 Merge pull request #3508 from YosysHQ/aki/rm_protobuf
7a73133c9f backends: protobuf: removed protobuf backend
03df1ac72b fix whitespace
e8ce9442a6 Merge pull request #3452 from ALGCDG/master
d68013811f Merge pull request #3507 from YosysHQ/claire/verificlibopt
090228a6a1 Fix handling of verific -L options, add implicit "-L work"
0e13d7e4c7 Bump version
ae1a24d0c4 Merge pull request #3503 from jix/abort_on_log_error
0113f44faa Reenable existing equiv_opt tests
81906aa627 Fix tests for check in equiv_opt
0516307637 Add "check -assert" to equiv_opt
f0478c520d Re-enable opt_dff_sr equiv_opt checks
afa5e6bb53 Exclude primary inputs from quiv_make rewiring
381ce66f58 Revert "Merge pull request #641 from tklam/master"
925f92918a clk2fflogic: Always correctly handle simultaneously changing signals
ac906d15ce Add YOSYS_ABORT_ON_LOG_ERROR environment variable for debugging.
c4a52b1b02 Bump version
a5172df9e9 Next dev cycle
f109fa3d4c Release version 0.22
7db26a8e59 Update CHANGELOG
11203815a8 Merge pull request #3500 from nakengelhardt/mutate_warn_not_enough
47e73826e0 mutate: warn if less mutations possible than number requested
b5d3920bf5 Merge pull request #3499 from YosysHQ/micko/verific_edif
620af8b663 Bump version
1a6f10e8ba Add support for EDIF file reading using Verific
f5e2c0a498 Merge pull request #3494 from YosysHQ/micko/verific_attributes
d29606532a Changing error reason string to be based on lut input plane limit constant.
43267dec99 support file content redirection for verific frontened
b45517f7b7 Add comment for future self
f54ac8a6d6 Handle attributes imported from verific
a9795c4fce Bump version
b2ddd0d42d Merge pull request #3489 from hzeller/20220924-fix-hardcoded-bin-bash
f09bf58b6e Fix hard-coded path to /bin/bash -> /usr/bin/env bash
fcd1be1422 Merge pull request #3486 from daglem/fix-flowmap-crash
0ab726e204 Bump version
69787f1906 remove extra space in formating
bc1e579483 stat: add tech tech-specific utilizations to json
50e267eace Bump version
5580185228 Merge pull request #3488 from YosysHQ/micko/test_fix
b2eb331b83 Merge pull request #3487 from YosysHQ/micko/verific_mem_fix
8fb498744f Import memory attributes
1ecf6aee9b Test fixes for latest iverilog
c4c68e8d86 Fix crash in flowmap
a217450524 Bump version
da614fe13a Fix tmpdir naming when passing -nocleanup option to abc(9) on systems where base_tmpdir isn't /tmp/
dd4a0c3034 Add CodeQL
d98738db5c Bump version
5ccc941f25 Update to latest ABC changes
406e12d859 Bump version
b7bf685010 Update to latest abc
3f94f9313a verific: better fix for read callback
06a9c7499a verific: fix crash when using prep right after read
4fa4161aa6 Bump version
07d9924a1b Next dev cycle
e6d2a900a9 Release version 0.21
0ff129c10b Update Changelog
6d5adb6a65 Update documentation
9313549cdd Bump version
3f04931adb Replaced old markdown Issue template with new GitHub forms templates (#3468)
1bc6ea2366 Merge pull request #3470 from jix/smtbmc-faster-parse
1d40f5e8fa smtbmc: Avoid unnecessary string copies when parsing solver output
6e907acf86 Bump version
d8a383b555 Merge pull request #3087 from tgingold-cern/sf2
d829d7fe00 Merge pull request #3458 from QuantamHD/abc_faster
1e0e3bd48e sf2: add NOTES about using yosys for smartfusion2 and igloo2
0f6cf8b8e4 sf2: add a test for $alu gate
c25f3ff3df sf2: suport $alu gate and ARI1 implementation
13ccdd032d synth_sf2: purge on last clean
39993a92d7 sf2/cells_sim.v: add XTLOSC, SYSRESET cells
1c0119aa90 sf2/cells_sim.v: add IOSTD parameter to I/O cells
4543751a77 synth_sf2: add -discard-ffinit option to discard ff initial value
7117817dbe Bump version
a8506c1c76 Merge pull request #3463 from YosysHQ/micko/hierarchy_fix
5b5fe76966 Add test for bug 3462
883831bd24 Fix mingw build
4bc1e1d1f1 Makes sure to set initial_top when change, fixes #3462
060cbd3e9e Bump version
0d8ee63d03 Merge pull request #3461 from YosysHQ/aki/hashlib_assert
6717e02023 kernel: hashlib: cleaned up message about table size in cases where `sizeof(int) == 4`, (closes #3440)
7d35003c16 Merge pull request #3449 from YosysHQ/aki/show_pathrw
e3eb114e75 use inttypes format specifiers
7e92e80741 dump runtime information for passes to json
8e640663d6 Merge pull request #3457 from KrystalDelusion/docs_width
114253cd54 Improves ABC command runtime by 10-100x
9465b2af95 Fitting help messages to 80 character width
1433a63165 yosys: passes: cmds: show: added filename re-writing to `show -lib`
15a0697c70 Adding check for BLIF names command input plane size.
db73f3c26b Merge branch 'master' of https://github.com/ALGCDG/yosys
029c2785e8 Bump version
f1c9399b66 Merge pull request #3450 from jix/write_aiger_nonff
5142fb3b5c write_aiger: Fix non-$_FF_ FFs
1c36f4cc2c Bump version
556d008ed3 Merge pull request #3434 from jix/witness_flow
f7023d06a2 sim: -hdlname option to preserve flattened hierarchy in sim output
66f761a8c5 smtbmc: Set step range for --yw and dont skip steps for --check-witness
927af914f1 Update CEX minimization patches for abc
4ad13c647e clk2fflogic: Generate less unused logic when using verific
65145db7e7 rename: Add -witness mode
b156fe903f yosys-witness: Add stats command
475267ac25 smtbmc: Add --check-witness mode
efd5b86eb9 aiger: Add yosys-witness support
f041e36c6e smtbmc: Add native json based witness format + smt2 backend support
96a1173598 btor: Support $anyinit cells
5893cae647 aiger: Support $anyinit cells
021c3c8da5 smt2: Support $anyinit cells
a2f9ebe43a memory_map: Add -formal option
0cdb14df41 setundef: Do not add anyseq / anyconst to unused memory port clocks
428ad5b9fd wreduce: Keep more x-bits with -keepdc
95db5a9d38 formalff: New -setundef option
a5e1d3b997 formalff: Set new replaced_by_gclk attribute on removed dff's clks
c0063288d6 Add the $anyinit cell and the formalff pass
c26b2bf543 Bump version
6f439dc59a Merge pull request #3425 from YosysHQ/lofty/stat-json
59facfa98c stat: add option for machine-readable json output
63fca0dbc2 Merge pull request #3277 from YosysHQ/lofty/rename-scramble_name
91010449ff Bump version
0b0e01e211 Merge pull request #3443 from YosysHQ/micko/resetall_undefineall
b76c72056b set default_nettype to wire for resetall
545a3417c8 resetall does not affect text defines, but undefineall does
51f67e55f2 Merge pull request #3322 from Forty-Bot/default_assignment_first
8c05f14b58 Order ports with default assignments first
035d99f3a8 Bump version
8fab6ec023 nexus: Fix BRAM mapping.
594cfd1d4d Merge pull request #3441 from YosysHQ/micko/smtio-utf-8
4444d5cf68 Switched to utf-8 in smtio.py
99f1c71582 properly encode string in rtlil
d2b4246a6d Bump version
6b4dbf6c36 Merge pull request #3439 from YosysHQ/micko/filepath_improve
f4a1906721 support file locations containing spaces
a48dcd1d40 rename: add -scramble-name option to randomly rename selections
6c65ca4e50 Encode filename unprintable chars
2b1aeb44d9 verific - make filepath handling compatible with verilog frontend
60a787fa50 Bump version
733902c81e Next dev cycle
4fcb95ed08 Release version 0.20
a07b06d5e7 Update Changelog
3f7042d114 update manual to latest
3705d8414e Merge pull request #3432 from YosysHQ/aki/jny_updates
6a1d98b816 Update manual and changelog
e989313317 Bump version
b8316b2f13 Merge pull request #3433 from jix/fix_smt_shift
6af5e74f95 smt2: Fix $shift/$shiftx with negative shift ammounts
e3074c044a misc: Added JNY schema definition
4f0ee383c9 backend: jny: updated the `JnyWriter` to emite a new "invocation" entry as well as a "$schema" entry to point to the location the schema will be at
7d4f87d69f Bump version
15393442d6 Merge pull request #3089 from YosysHQ/gatecat/liberty_wb
a207fd4b33 Merge pull request #3429 from YosysHQ/micko/verific_upto
6f792e2223 Update documentation
52a4a89265 Setting wire upto in verific import
30a4218f53 Bump version
d19f9d0b66 Update README
23a39d707e Bump version
a681904237 Assorted microoptimization speedups in core data structures.
6ba48515b5 macos 10.15 deprecated by gh actions
29a5947bf8 Make all compile under OpenBSD (#3423)
bc012995b4 Support using ABC source tarball distribution
d4875ceae6 Merge pull request #3406 from josuah/master
358e656e21 Bump version
f679b756d8 opt_reduce: Fix use-after-free.
7e02b6a70b Bump version
12b0ce9721 Merge pull request #3419 from jix/sim_nested_anyseq
14ba50908b sim: Fix $anyseq in nested modules
58fddf61cc reduce the Makefile TCL compatibility code
6eba56fcf0 include changes to support OpenBSD and prepare NetBSD support
793b9ade56 extends the list of platforms without <alloca.h>
a82eff2e20 Bump version
d25f349f4d Update to latest abc
08c319fc35 Bump version
f086da8bdf Merge pull request #3392 from rockybulwinkle/rockybulwinkle-patch-1
58c51b9a0b Remove empty lines
2326b9f90a Bump version
933f110bf7 Merge pull request #3404 from YosysHQ/fix-build-after-pr-3399
502b96fe53 Fix external ABC build after commit 0ca0932b5.
43d86f2c26 Fix WASI build after commit 0ca0932b5.
09c6fc68c7 Bump version
0098b32c6c using more portable formatting
0cd20693c2 Merge pull request #3399 from YosysHQ/abc_cpp
4c5152bf26 Merge pull request #3402 from C-Elegans/modfloor_support
86a4ba1758 Merge pull request #3397 from pepijndevos/patch-2
24b895778a Add support for GHDL modfloor operator
086c2f3224 Bump version
4db820e9d4 Fix static initialization, fixes mingw build
0ca0932b52 Update abc and build as C++
da0682b99a Next dev cycle
a45c131b37 Release version 0.19
0b44bff182 Merge pull request #3398 from jix/mention_smtlib2_module
5343911263 Mention smtlib2_module in README.md and CHANGELOG
59b96bb1f8 Upadte documentation and changelog
de07eb11c1 Apicula now supports lutram
c39bade1a7 Bump version
4a1e54bf70 Merge pull request #3395 from jix/opt_dff_keepdc_initival
876ef59f4f Merge pull request #3396 from jix/async2sync_const_clocks
fda3a537e1 Update abc
0182b26aba Merge pull request #3391 from programmerjake/simcheck-allow-smtlib2-blackboxes
42721b6a12 Bump version
5db542742b async2sync: turn FFs with const clks into gclk FFs with feedback
b80976b543 Update to new verific extensions inteface
9d63a90e0e Bump version
0d2377c8a6 Merge pull request #3394 from jix/memory_map_rom_keepdc
930bcf0e75 smt2, btor: Revert calling memory_map -rom-only
a47254bd10 opt_dff: With -keepdc, never turn undef init vals into const drivers
a6b440b5c9 memory_map: avoid undriven unused FF inputs for -keepdc
869e6a1b6d Bump version
d78d807a7f memory_map: -keepdc option for formal
48efc9b75c gatemate: Add test for LUT tree mapping
38a24ec5cc gatemate: Add LUT tree library script
7c756c9959 gatemate: Add preliminary sim models for LUT tree structures
fbf5d89587 equiv_make: Add -make_assert option
ec2f8796bd Update tcl doc, yosys does not return data to tcl
c16c028831 add hierarchy -smtcheck
b2408df313 Bump version
f69c2c802c Adding expected error message.
c8cd4f468a Adding testcase for issue 3374
7eeb656e2a Add check for BLIF with no model name
1fdbb42fdd Revert "use new verific extensions library"
a30b38910c Merge pull request #3387 from ekiwi/btor-pos-cell
0b486c56e8 Bump version
de5c4bf523 btor: add support for $pos cell
e7e8e3b0f6 Adding expected error message.
34804f3fb6 codeowners: adopt ABC9 and update intel_alm username
5dfad5101d chformal: Rename -coverprecond to -coverenable
e39c422734 chformal: Test -coverprecond and reuse the src attribute
c659bd1878 chformal: Add -coverprecond option
90147f5fbf Bump version
4542d51791 Adding testcase for issue 3374
e6a5d84149 Merge pull request #3383 from jix/write_formal_map_roms
4adef63cd4 smt2, btor: Use memory_map -rom-only to make ROMs usable for k-induction
ab3a9325c3 memory_map: Add -rom-only option.
c23139fd98 Merge pull request #3382 from YosysHQ/micko/verific_extensions
607e957657 use new verific extensions library
01daa077a2 memory_map: Use const drivers instead of FFs for ROMs.
bb634d39ef Bump version
d69091806a memory_libmap: Fix wrprio handling.
25a4cd7020 memory_libmap: Fix params emitted for unused ports for consistency.
b604c97b33 Add check for BLIF with no model name
3046a06490 Bump version
6b7efe12b7 Add a check for packed memory MEMID uniqueness
3eaa9e38e0 Merge pull request #3196 from bfg86/bfg86/rename
1ff0e1a58a opt_ffinv: Fix use after free.
ddc8044655 removed deprecated features code
aedd3b7999 Updating help-text with nakengelhardts suggestion.
b15a46c2c0 Bump version
53b205c41d Merge pull request #3368 from jix/smtbmc-unroll-noincr-traces-fix
4b423dcfb4 Next dev cycle
19ce3b45d6 Release version 0.18
d1cd24a457 Update manual
1940bf647f Updated CHANGELOG
47a99092af Bump version
b8ede6162b Merge pull request #3349 from nakengelhardt/select_count_scratchpad
871b277d35 Merge pull request #3359 from jix/fmcombine-memid
9c41b43191 Use compiler-generated default constructor for RTLIL::Const::Const
9d41aa8e28 Avoid unnecessary copy of a potential large constant value.
6e8e4b4550 verific: Added "-vlog-libext" option to specify search extension for libraries
d1b2beab12 Bump version
47efc04a7d wreduce: Introduce -mux_undef option (aligned with opt_expr).
0c5f62f6ff smtbmc: noincr: keep solver running for post check-sat unrolling
6db2948938 Merge pull request #3357 from jix/smtbmc-cvc5
a0172e68c5 More updates on CHANGELOG
096f3d2aa4 Update changelog and manual
aae2c01326 sta: warn on unrecognised cells only once
4afb951283 Bump version
d9bb10ba5f Merge pull request #3367 from jix/smtlib2-module-fixes
ac22f1764d smt2: emit smtlib2_comb_expr outputs after all inputs
5f9a97d234 Merge pull request #3319 from programmerjake/smtlib2-expr-support
fe048a48b3 Merge pull request #3358 from jix/smtbmc-yices-forall
d07828b409 opt_ffinv: Harden against simple ff/inv loop.
9e8a2ac051 iopadmap: Fix z assignment removal.
aa0b47c74a Bump version
e35a166353 verific: proper file location for readmem commands
8d0f71b256 Bump version
459941c8ff fmcombine: Add _gold/_gate suffix to memids
ab9e887dee smtbmc: Force nonincremental mode when yices is used with forall
0207d7b0cf smtbmc: recognize cvc5 and fix unrolling for cvc4/cvc5
0b0123e003 don't use sed -i because it won't work on macos
d88a5d26b7 Fix preventing show crashing with newer graphviz
b7c19b1c88 smtlib2_module: try to fix test on macos
cd57c5adb3 smt2: Add smtlib2_comb_expr attribute to allow user-selected smtlib2 expressions
1eb1bc441b Bump version
71dfbf33b2 Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}.
3a0aa9c663 memory_dff: Add support for no_rw_check attribute.
61b05051e1 also make 'stat' save counts to scratchpad
a55c3db384 have 'select -count' save the count to scratchpad entry 'select.count'
01cb02c81d Merge pull request #3348 from zachjs/func-tern-hint
a79a228c2b Bump version
a650d9079f verilog: fix width/sign detection for functions
cea7e85d60 Merge pull request #3347 from DanielHuisman/fix-3053
6809ee8de0 Fix typo in emcc flags (typo introduced by #3053)
4bfaaea0d5 verilog: fix size and signedness of array querying functions
ce24208a8b Bump version
5d08688054 gatemate: Fix minor issues with `memory_libmap` (#3343)
197c9e04e8 Merge pull request #3333 from mohamed/feature/tmpdir
08275a1569 Cleanup, and fix windows
1822be8792 Observe $TMPDIR variable when creating tmp files
bf78041e89 Merge pull request #3341 from mmicko/unused_vars
f9b6fe521d Upload emscripten artifact
4316cdb603 Remove set but unused variable
5490f94e82 Add emcc build (stuck if all cpus used on GH)
0d31aa6008 Proper std::move
7ee570a75e Use proper operator
b0c71ed594 Merge pull request #3053 from DanielHuisman/pr-2
f698a0514d Bump version
b75fa62e9b verilog: fix $past's signedness
63c9c9be5c Merge pull request #3011 from DanielHuisman/pr-1
8e9471c695 Merge pull request #3335 from programmerjake/divfloor-in-write_smt2
904e2efe11 Merge pull request #3138 from DanielG/fix-git-rev
222e7a2da3 Make GIT_REV logic work in release tarballs
cffec1f95f verilog: fix signedness when removing unreachable cases
d53479a0d6 add $divfloor support to write_smt2
c525b5f919 Bump version
335b4888ce Merge pull request #3332 from YosysHQ/verific_f
fdb393b6ce fix text to fit 80 columns
4a5790d404 Update verific command file documentation
a6ec5754c6 Use analysis mode if set in file
e47cfe277e Merge pull request #3331 from YosysHQ/git_rev_fix
87149b3f8e Change way to get commit sha
166a175983 abc9_ops: Don't leave unused derived modules lying around
0b1a1a576b Bump version
795c445159 Merge pull request #3324 from jix/confusing-select-errors
fc65ea47df select: Fix -assert-none and -assert-any error output and docs
015ca4ddac Bump version
606f1637ae Add memory_bmux2rom pass.
982a11c709 Add memory_libmap tests.
2a2dc12eb6 gatemate: Use `memory_libmap` pass.
2dcb0797f0 machxo2: Use `memory_libmap` pass.
9d11575856 efinix: Use `memory_libmap` pass.
f4d1426229 anlogic: Use `memory_libmap` pass.
d7dc2313b9 ice40: Use `memory_libmap` pass.
3b2f95953c xilinx: Use `memory_libmap` pass.
e4d811561c gowin: Use `memory_libmap` pass.
0a8eaca322 nexus: Use `memory_libmap` pass.
a04b025abf ecp5: Use `memory_libmap` pass.
7c5dba8b77 Add memory_libmap pass.
9450f308f0 proc_rom: Add special handling of const-0 address bits.
06ef3f264a Bump version
7c64c70727 Merge pull request #3310 from robinsonb5-PRs/master
98c7804b89 opt_ffinv: Use ModIndex instead of ModWalker.
6c6017c973 Use log_warning when Tcl_Init fails, report error with Tcl_ErrnoMsg.
2864f2826a Merge pull request #3314 from jix/sva_value_change_logic_wide
3f8fb28cd2 Bump version
2858bb03cd Add opt_ffinv pass.
f56a3bd48f Bump version
990c9b8e11 Add proc_rom pass.
fada77b8cf verific: Use new value change logic also for $stable of wide signals.
83dbea1689 Now calls Tcl_Init after creating the interp, fixes clock format.
c862b1dbfb Bump version
587e09d551 Merge pull request #3305 from jix/sva_value_change_logic
5ca2ee0c31 Merge pull request #3297 from jix/sva_nested_clk_else
a855d62b42 verific: Improve logic generated for SVA value change expressions
d562bfd165 Next dev cycle
6f9602b4cf Release version 0.17
72d2efeb32 Update CHANGELOG
65f70b9d50 Update manual
58b23954e8 Merge pull request #3299 from YosysHQ/mmicko/sim_memory
600079e281 Fix running sva tests
9c69e9f8a6 Bump version
77b1dfd8c3 opt_mem: Remove constant-value bit lanes.
048170d376 Bump version
37b6614718 include latest abc changes
7fcf976f9e include latest abc changes
384d2120ee Merge pull request #3300 from imhcyx/master
52d8ddee0c Include abc change to fix FreeBSD build
d8adbff72f Handle possible non-memory indexed data
71166eeecf memory_share: fix wrong argidx in extra_args
a8cc0c3930 Bump version
18a48b1337 abc: Use dict/pool instead of std::map/std::set
8b3657454b map memory location to wire value, if memory is converted to FFs
8e02b3ca30 fix crash when no fst input
ad48639cdd Start restoring memory state from VCD/FST
3fb32540ea Add propagated clock signals into btor info file
96f64f4788 verific: Fix conditions of SVAs with explicit clocks within procedures
11e75bc27c Bump version
3730db4b98 AIM file could have gaps in or between inputs and inits
c785cb7fe3 Bump version
7bdf7365e7 Merge pull request #3294 from YosysHQ/micko/verific_merge_past_ff
422db937d4 Ignore merging past ffs that we are not properly merging
b30d90a14a Bump version
414dc25a96 Add missing parameters for ecp5
6ae0b51c76 Merge pull request #3287 from jix/smt2-conditional-store
e0e31bfc5c Merge pull request #3257 from jix/tribuf-formal
3c0f3504c6 Merge pull request #3290 from mpasternacki/bugfix/freebsd-build
a511c27eb7 Merge pull request #3289 from YosysHQ/micko/sim_improve
0302e97ebc Fix build on FreeBSD, which has no alloca.h
bbfdea2f8a Match $anyseq input if connected to public wire
4d80bc24c7 Treat $anyseq as input from FST
9c7deabf94 Ignore change on last edge
33f4009bb5 Last sample from input does not represent change
83cad82b29 latches are always set to zero
c989adcc2d If not multiclock, output only on clock edges
75032a565d Set init state for all wires from FST and set past
8fa2f3b260 Fix multiclock for btor2 witness
c7ef0f2932 smt2: Make write port array stores conditional on nonzero write mask
29c0a59589 Bump version
c3a3f68b4d Merge pull request #3280 from YosysHQ/micko/fix_readaiw
2610b04033 Update abc
1cc281ca6f verific: allow memories to be inferred in loops (vhdl)
d23260d381 Merge pull request #3282 from nakengelhardt/verific_loop_rams
36b5caf821 Bump version
25ff83f0b5 memory_share: Fix up mismatched address widths.
48eea3efcf opt_dff: Fix behavior on $ff with D == Q.
57bc29c64a verific: allow memories to be inferred in loops
9508bb2330 Fix reading aiw from other solvers
bc48500548 tribuf: `-formal` option: convert all to logic and detect conflicts
c1646a00ac Bump version
4772bc70d0 Merge pull request #3275 from YosysHQ/micko/clk2fflogic_fix
868409361c Use wrap_async_control_gate if ff is fine
bd7ee79486 Merge pull request #3273 from modwizcode/fix-build
1f1a403cce pass jny: flipped the defaults for the inclusion of various bits of metadata
6053856f91 pass jny: ensured the cell collection is cleared between modules
5a016713cc pass jny: fixed missing quotes around the type value for the cell sort
2e792857e9 pass jny: fixed the backslash escape for strings
cae5ea8337 pass jny: removed the invalid json escapes
dccc89e8b3 pass jny: added some todo comments about things that need to be done before a proper merge, but it should be enough for the PoC at the moment
1be9bef28b pass jny: changed the constructor initializers to use parens rather than curly-braces to hopefully make GCC 4.8 happy
43b2fc5566 pass jny: fixed the string escape method to be less jank and more proper
52ea944012 pass jny: fixed the signed output for param value output
58e2870261 pass jny: added connection output
167206f2f5 pass jny: added filter options for including connections, attributes, and properties
587f31b9a3 pass jny: large chunk of refactoring to make the JSON output more pretty and the internals less of a spaghetti nightmare
0e20619189 metadata -> jny: migrated to the proper name for the pass
bdf14557ca pass metadata: added the machinery to write param and attributes
1876ed21e7 pass metadata: removed superfluous `stringf` calls
ca03fbdc6d pass metadata: some more rough work on dumping the parameters and attributes
6a90b42c48 pass metadata: fixed the MetadataWriter object initializer so GCC 4.8 is happy
7a275567df pass metadata: added the output of parameters,
d8b85e1247 pass metadata: fixed some of the output formatting
f6bb238051 pass metadata: initial commit of the metadata pass for exporting design metadata for yosys assisted tooling
ccc6060f52 Makefile: properly conditionalize features requiring compression.
e0ba324236 Bump version
8a1d531b25 Merge pull request #3269 from YosysHQ/micko/fix_autotop
376d8cb26f abc: Add support for FFs with reset in -dff
4da3f2878b Bump version
bf15dbd0f7 sv: fix always_comb auto nosync for nested and function blocks
977002b1d2 Reorder steps in -auto-top to fix synth command, fixes #3261
957fdb328a Next dev cycle
b63e0a0cae Release version 0.16
580800eb0d Bump version
0aec79a0da show: Fix width labels.
0d3bf9e725 Update CHANGELOG and manual
75f4847689 Merge pull request #3265 from YosysHQ/micko/sim_improvements
6020ba67ac past_ad initial value setting
2c96ecc5f7 setInitState can be only one altering values
b54aecd80a Set past_d value for init state
8ca9737180 Merge pull request #3264 from jix/invalid_ff_dcinit_merge
5ac5c57c73 Bump version
ca5b910296 opt_merge: Add `-keepdc` option required for formal verification
2a76af9eb6 Merge pull request #3263 from YosysHQ/micko/clk2ff_init
86ce441af6 Set init values for wrapped async control signals
2ec4af56e6 Merge pull request #3262 from YosysHQ/micko/verific_hiernet
1a1f529099 Preserve internal wires for external nets
2b115d858d Bump version
ed83f0dea8 Merge pull request #3256 from YosysHQ/micko/aiw_multiclock
c95b9b4ba5 Support memories in aiw and multiclock
fc2af4e32d Bump version
18fb73fd89 Merge pull request #3259 from YosysHQ/micko/verific_valgrind
bbf65702a1 Fix valgrind tests when using verific
0921e5b9a4 Merge pull request #3260 from YosysHQ/micko/proper_scopename
2e47b61cc6 Proper scope naming from FST
72e5498bdf Merge pull request #3250 from YosysHQ/micko/verific_consistent
c662fcbc5c Bump version
d44f618de5 Merge pull request #3258 from jix/fix-no-assertions
8b15f3a548 smtbmc: fix bmc with no assertions
48d7a6c477 Bump version
3bebe17e5d kernel/mem: Only use FF init in read-first emu for mem with init
8cc8c5efde Merge pull request #3253 from jix/smtbmc-nodeepcopy
17e2a3048c Merge pull request #3247 from jix/smtbmc-keepgoing
c1057cb3e0 Merge pull request #3194 from Ravenslofty/abc9-flow3mfs
421192f1cb Merge pull request #3246 from YosysHQ/gatecat/timing-derive-fix
30bc0d26ea gowin: Add oscillator primitives
d25daa6203 smtbmc: Avoid unnecessary deep copies during unrolling
62b89bb0d4 Update URL to zlib
703769e494 Properly mark modules imported
207417617d Bump version
349c0ff0a7 Add some more reserve calls to RTLIL::Const
a7e7a9f485 Merge pull request #3249 from YosysHQ/micko/no_startoffset
245ecb0529 Import verific netlist in consistent order
4fd8b38d7a Add -no-startoffset option to write_aiger
afe258e6f8 Bump version
89dcd7c31e Merge pull request #3243 from nakengelhardt/fix_aiw_comment
5e4d804e53 yosys-smtbmc: Option to keep going after failed assertions in BMC mode
e43ebf8527 yosys-smtbmc: Fix typo in help text, remove trailing whitespace
8b64dc1dce abc9_ops: Also derive blackboxes with timing info
a7ee01065a ignore # comment lines
6318db6152 Bump version
15c7205908 Update abc with latest fix
322ab1cd54 Proper SigBit forming in sim
ff3b0c2c46 Proper SigBit forming in sim
f45b290820 Bump version
be9595e18f xilinx: Add RAMB4* blackboxes
3bf1070245 Bump version
55eed8df57 More verbose warnings
0c5279b73d Merge pull request #3236 from YosysHQ/micko/tb_initial
e1d4863a19 Bump version
1f3423cd7d Recognize registers and set initial state for them in tb
e217e3017a Update sim help message.
66914b6eb3 Bump version
19b7633aca gowin: add support for Double Data Rate primitives
25d6fdfea7 Merge pull request #3232 from YosysHQ/micko/fst2tb
f5c20b8286 Added fst2tb pass for generating testbench
5e2992dae2 Merge pull request #3213 from antonblanchard/abc-typo
27c5bafc95 Proper example code
a502570c25 Bump version
cbece4af0c Merge pull request #3229 from YosysHQ/micko/sim_date
532343dcfa Merge pull request #3222 from zachjs/prune-linux-ci
04de9bb655 Merge pull request #3228 from YosysHQ/micko/disable_tests
e21badd4b3 Add "sim -q" option
37de369ba7 Add date parameter to enable full date/time and version info
be32de1caa Small fix in "sim" help message
2f44683f4f Merge pull request #3226 from YosysHQ/micko/btor2witness
5204694123 FstData already do conversion to VCD
b72c779204 Support cell name in btor witness file
d340f302f6 Fix handling of some formal cells in btor back-end
ebe2ee431e handle state names of $anyconst and $anyseq
5e7ea57d8e Prune Linux CI builds
357336339a Proper write of memory data
75c0391f06 Disable tests on most of platforms
eb8c61f033 Bump version
9f7a55c99f intel_alm: M10K write-enable is negative-true
295b0d1899 Start work on memory init
f37ac5d934 Fixes and error check
ede348cdc2 cleanup
1b1ecd4ab0 Error checks for aiger witness
b6aca1d743 btor2 witness co-simulation
4ccc2adbda Merge pull request #3210 from rqou/json-signed
7ba636cb32 Bump version
a95e5d505b Merge pull request #3186 from nakengelhardt/smtbmc_sby_print_id
13655ddccf Merge pull request #3206 from YosysHQ/micko/quote_remove
c3124023e4 Merge pull request #3207 from nakengelhardt/json_escape_quotes
7be7f5e02e Next dev cycle
07a43689d8 Release version 0.15
66ba5ed7a5 Update ABC
a7090e9711 Update documentation
9581b9adac Merge pull request #3219 from YosysHQ/micko/quick_vcd
d1fbe738a7 Merge pull request #3220 from YosysHQ/claire/simstuff
e768f7552c Bump version
59983eda17 Add option to ignore X only signals in output
48b56a4f7f Write simulation files after simulation is performed
3818e1160d Update CHANGELOG
2ca69e1b88 Merge pull request #3224 from YosysHQ/micko/refactor
28bc88a57e Cleanup
4a38d15f0d Bump version
94505395a9 Refactor sim output writers
dfd4c81eac Quick fix
56b968f61c Add writing of aiw files to "sim" command
1fd3a642c9 Hotfix in AIGER witness reader state machine
8be09b5b24 VCD reader support by using external tool
ec4af6af2f Merge pull request #3216 from YosysHQ/claire/simstuff
9571acc0bf Support extended aiw format
fca168797e Fix for last clock edge data
ca261d3c28 Experimental sim changes
08c771078f Bump version
22d9bbb308 gowin: Remove unnecessary attributes
9b3cd4f0d8 gowin: Add support for true differential output
89300b2dca abc: Fix {I} and {P} substitution
dc739362c7 print cell name for properties in yosys-smtbmc
a41c1df76f Merge pull request #3211 from YosysHQ/micko/witness
ac294ed419 Merge pull request #3197 from YosysHQ/claire/smtbmcfix
2d3a337795 json: Add help message for `signed` field
286caa09bd Bump version
d0b72e75d9 Merge pull request #3203 from YosysHQ/micko/sim_ff
d0f4d0b153 ecp5: Do not use specify in generate in cells_sim.v.
fd3f08753a Fix handling of ce_over_srst
8fd1b06249 fix handling of escaped chars in json backend and frontend
1aa9ad25d0 Fix cycle 0 in aiger witness co-simulation
5f918803de Changed error message
41754b4207 Added AIGER witness file co simulation
13a5c28459 simplify logic of handling flip-flops and latches
61752b255f Review cleanup
29293a57bb Remove quotes if any from attribute
21baf48e04 test dlatchsr and adlatch
271ac28b41 Added test cases
fb22d7cdc4 Add support for various ff/latch cells simulation
1586000048 Bump version
c9a32c0d92 Merge pull request #3204 from YosysHQ/claire/update-abc
3bae2705fc Bump ABC version
426f89fc6f Bump version
15a4e900b2 verilog: support for time scale delay values
68c67c40ec Fix access to whole sub-structs (#3086)
59738c09be Bump version
3a62fa0c97 gowin: Add remaining block RAM blackboxes.
1772a1e98e Bump version
15eb66b99d verilog: fix dynamic dynamic range asgn elab
90bb47d181 verilog: fix const func eval with upto variables
ca876e7c12 Merge pull request #2376 from nmoroze/clk2ff-better-names
30eb7f8665 Add a bit of flexibilty re trace length when processing aiger witnesses in smtbmc.py
fc7d78f071 Merge pull request #3164 from zachjs/fix-ast-warn
49545c73f7 Merge branch 'master' into clk2ff-better-names
e016518866 Merge pull request #2019 from boqwxp/glift
7ac98d1c87 Add -suffix option to rename -wire.
5ac32ea68c abc9: add flow3mfs script
c8903e7053 Bump version
a08fff9c0f Merge pull request #3193 from YosysHQ/micko/verific_f
2cef48bf2c Add ability to override verilog mode for verific -f command
f61f2a4078 gowin: Fix LUT RAM inference, add more models.
ac2bb70b52 ecp5: Fix DPR16X4 sim model.
23d062fea3 Bump version
818060880d Next dev cycle
a4522d6282 Release version 0.14
9647f6326f Update CHANGELOG and manual
d7f7227ce8 Merge pull request #3185 from YosysHQ/micko/co_sim
9c93668954 Bump version
958c3a46ad nexus: Fix arith_map CO signal.
c0a156bcb4 Error detection for co-simulation
6db23de7b1 bug fix and cleanups
675a7bd22c Bump version
2d98fe870c Merge pull request #3183 from YosysHQ/micko/nto1mux
0b633b6c2e Use bmux for NTO1MUX
7ef6da4c7d Add test cases for co-simulation
518521c72e Merge pull request #3182 from yrabbit/wip-doc2
f5609d52c4 Correct a typo in the manual
4a30c9cb94 Fix Visual Studio build
990aee5531 respect hide_internal flag
169ffcd2fb unify cycles counting and cleanup
820b2fdd65 added stimulus mode and param check
0a6e2bd5d5 Update comment
e04ac4e9e9 Fix unextend method for signed constants
8ba2000a50 error when no signal found
bf85dfee5e Merge pull request #3176 from higuoxing/fix-ref-manual
1b5ff92e62 Cleanup
eabd0ff115 Compare bits when not all are defined
26de52fa09 Cleanup
6513300db7 message update
543feb75cb Display simulation time data
a6959d30df Use edges when explicit
cbadfa0268 Updating initial state and checks
190e44f0da Fix scope
fc40df0916 Bump version
56e7791760 verilog backend: Emit a `wire` for ports as well.
0520e99968 Fix the help message of synth_quicklogic.
07a657fb0c opt_reduce: Add $bmux and $demux optimization patterns.
772d137bfa Bump version
93508d58da Add $bmux and $demux cells.
f04d1398e5 check if stop before start
ecbba625c4 set initial state, only flip-flops
cb12b7c4d8 ignore not found private signals
f0f3c81c56 preserve VCD mangled names
72acce0c82 detect edges even when x
81b76155d6 recursive check
a8d03df173 cleanup
4f75a2ca1b Do actual compare
7101df62f8 Fix for limit_range_end when not writing vcd
3e35de2be1 Add more options and time handling
db33b1e535 opt_dff: Don't mutate muxes while ModWalker is active.
bac750fb99 kernel/mem: Add read-first semantic emulation code.
9a2294f285 Bump version
0e97c3fd74 manual: Fix a custom pass example.
1759c80a3f memory_bram: Make use of new mem emulation functions to map more RAMs.
5e4c6915c9 kernel/mem: Add functions to emulate read port enable/init/reset signals.
84f0df1c95 Bump version
76f7b030ae change to windows-2019
ccc3e3d13a update version
40018e191b Display values of outputs
226dc659f0 Fix tabs/spaces
be7be63fec Check if stimulated
9a8939f0a4 Read fst and use data to set inputs
8a02616465 Add fstdata helper class
c811a71301 Cleanup of config to support platforms
ccfc00705a Add ability to write to FST file
9e9083bbe9 Add FST library
bc027b2cae Bump version
f699c4ba58 nexus: Fix BB sim model
36482680d5 Removed dbits 8 since 9 will always be picked
4525e419f6 Merge pull request #3120 from Icenowy/anlogic-bram
342927732e fix dumpAst() compilation warning
59382945a9 Bump version
55924de708 Merge pull request #3162 from YosysHQ/mmicko/windows_guidelines
703306c119 Update guidelines/Windows
891eec2882 Merge pull request #3145 from nakengelhardt/advertise_suite_in_readme
15b4d05805 mention distributions' package manager
41e215219b Add info about VS build
61324cf55f Bump version
b91533d9f2 Forgot one
883b4fb7e6 Change url to https
c428a894c0 Next dev cycle
8b1eafc3ad Release version 0.13
64972360a8 Update CHANGELOG
0feba821a8 Bump version
aa35f24290 sv: auto add nosync to certain always_comb local vars
828e85068f sv: fix size cast internal expression extension
59a7150344 Bump version
66447e8faf logger: fix unmatched expected warnings and errors
b022fe61a7 opt_dff: fix sequence point copy paste bug
6483e691bc mention tabby+oss cad suite in readme
493b5e03e7 manual: Fix cell-stmt order
361916ad3e Bump version
e0e4dfb55e fix iverilog compatibility for new case expr tests
207af4196b fixup verilog doubleslash test
8c509a5659 sv: fix size cast clipping expression width
cb17eeaf50 Update manual
cfe940a98b Bump version
ebe396a2ab Merge pull request #3127 from whitequark/cxxrtl-no-reset-elided
fc049e84a9 cxxrtl: don't reset elided wires with \init attribute.
7407a7f3ef Bump version
d015c2b48a intel_alm: disable 256x40 M10K mode
229980d663 Bump version
f84c9d8e17 memory_share: Fix SAT-based sharing for wide ports.
f599c148c5 Bump version
7608985d2c fix width detection of array querying function in case and case item expressions
c2b7ad3b28 anlogic: support BRAM mapping
60c3ea367c Bump version
ed4642e18e Merge pull request #3115 from whitequark/issue-3112
73eea51613 Merge pull request #3114 from whitequark/issue-3113
4cd2f03e36 preprocessor: do not destroy double slash escaped identifiers
7f2ea7d222 cxxrtl: demote wires not inlinable only in debug_eval to locals.
4f1d62d9b2 bugpoint: avoid infinite loop between -connections and -wires.
477eeefd9b Bump version
5dadcc85b7 Merge pull request #3111 from whitequark/issue-3110
e1c7a9a647 Hotfix for run_shell auto-detection
48ed6d998b Fix null pointer dereference after failing to extract DFF from memory.
b07ca8756a Bump version
5e5c8a54ce Merge pull request #3108 from YosysHQ/claire/verificdefs
313340aed5 Add YOSYS to the implicitly defined verilog macros in verific
19a38222e7 Bump version
0aad88a2fb Add clean_zerowidth pass, use it for Verilog output.
bdc6ba019c Merge pull request #3105 from whitequark/cxxrtl-reset-memories-2
6a7253b46e Bump version
26f0f6bb0b Fix unused param warning with ENABLE_NDEBUG.
d019b4e681 rtlil: Dump empty connections when whole module is selected.
55c9fb3b18 cxxrtl: preserve interior memory pointers across reset.
21fbdb6638 Merge pull request #3103 from whitequark/write_verilog-more-zero-width-values
7c9e498662 cxxrtl: use unique_ptr<value<>[]> to store memory contents.
86f2804dc3 write_verilog: dump zero width sigspecs correctly.
8e91857fab Bump version
2412497c26 Merge pull request #3102 from YosysHQ/claire/enumxz
2da214d721 Fix verific import of enum values with x and/or z
f8978f9e0a Merge pull request #3097 from YosysHQ/modport
19773d093f Update verific.cc
ce82afe44f Merge pull request #3099 from YosysHQ/claire/readargs
d6e4d3f1ba Fix the tests we just broke
ce08046f44 Added "yosys -r <topmodule>"
0cbdb42dcd Use "read" command to parse HDL files from Yosys command-line
cdb5711875 Bump version
1184a7f3b4 opt_mem_priority: Fix non-ascii char in help message.
b06f547993 If direction NONE use that from first bit
d186ea7a2d Bump version
c23cd00f30 Next dev cycle
2156e20db5 Release version 0.12
71e762d68c Update manual
d65942b9ac Add gitignore for gatemate
3ebfa3fb84 Make sure cell names are unique for wide operators
2be110cb0b Bump version
4792d925fc Update CHANGELOG and CODEOWNERS
707d98b06c Bump version
b506f398dd Add read_liberty -wb
a31c8a82be intel_alm: preliminary Arria V support
77327b2544 sta: very crude static timing analysis pass
113c943841 Bump version
d0fda4c0ef Merge pull request #3080 from YosysHQ/micko/init_wire
c081c683a4 Give initial wire unique ID, fixes #2914
07dde32bf1 Bump version
fdb19a5b3a Support parameters using struct as a wiretype (#3050)
06bddb5e49 Bump version
cb41209095 synth_gatemate Revert cascade A/B port mixup
decdc743db synth_gatemate: Remove iob_map invokation
0d871b6c49 synth_gatemate: Add block RAM cascade support
285ec0547b synth_gatemate: Remove obsolete iob_map
81964d6d6f synth_gatemate: Update pass
74aee88e81 synth_gatemate: Remove specify blocks
05f24adca9 synth_gatemate: Remove gatemate_bramopt pass
97d03c2b3b synth_gatemate: Apply new test practice with assert-max
76bf96d310 synth_gatemate: Fix fsm test
4bee908ae8 synth_gatemate: Revise block RAM read modes and initialization
3f4ccdf2f5 synth_gatemate: Remove unsupported FF initialization
d592bd93b8 synth_gatemate: Rename multiplier factor parameters
6825de6343 synth_gatemate: Registers are uninitialized
acb993b27b Allow initial blocks to be disabled during tests
0a72952d5f synth_gatemate: Apply review remarks
cfcc38582a synth_gatemate: Apply review remarks
240d289fff synth_gatemate: Initial implementation
b3e2001e1f Bump version
107aad2cd2 show: Fix wire bit indexing.
48a628522b update abc
b4f68e3cca Update abc
1df8ac58fe Bump version
a6c90c9772 Merge pull request #3075 from YosysHQ/micko/verific_mem_size
4699ddcc1b Merge pull request #3077 from YosysHQ/claire/genlib
c77d5a2aac Spelling fix in abc.cc
093e287a1e Add genlib support to ABC command
506acd52de iopadmap: Fix ebmarassing typo
15a35f5584 No need to alocate more memory than used
224c6f8664 Bump version
f4f5acf396 genrtlil: Fix displaying debug info in packages
15b0d717ed iopadmap: Add native support for negative-polarity output enable.
4871d8f199 Bump version
cd71d260ea Update CODEOWNERS
cd3f3d5df0 Limit macOS GH actions
d39d4e11d2 Bump version
4bf8deacbb synth_gowin: move splitnets to after iopadmap (#2435)
9a413803eb manual: fix pdflatex inputenc undefined char error
a3eec687e0 Remove noalu from synth_gowin json output as Apicula now supports it
781cf13abd Bump version
0c7461fe5e gowin: widelut support (#3042)
8f08908d8d Bump version
a28ee81be0 Next dev cycle
360fed8e4d Release version 0.11
18bcf820b3 Must use latest flex to generate c++17 compatible code
d5de2a0cdb Make it work on all
cbb6887ac8 Correct way of setting maybe_unsused on labels
051b234df6 Add missing changelog item
598f51c6a1 Update command reference
5a5244a12e Merge pull request #3067 from YosysHQ/aki/ci_update
d67eb0eb1c Removed semicolon from macro
11e58d5415 Bump version
f346868ccc flatten: Keep sigmap around between flatten_cell invocations.
9cb5092ad1 Bump version
5b834d3aff Merge pull request #3068 from YosysHQ/claire/verific_cfg
2ea757da51 Add "verific -cfg" command
97fce665c7 Bump version
e1cfd37384 ci: removed the old `test.yml` workflow, as it was replaced by `test-linux.yml` and `test-macos.yml`
1e7ba922e5 ci: expanded the macOS tests suite to cover more compilers and C++ versions
ff31af6d72 ci: expanded the Linux test suite to cover more compilers and C++ versions
ad81cff823 Changed the Makefile to have an explicit `CXXSTD` parameter which allows for the setting of other C++ standards, the default is `c++11`
dd06d23649 Merge pull request #3066 from YosysHQ/claire/verific_gclk
83118bfb9e Fix verif…
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Description
Added the option to load external clustering attraction data
Checklist:
There are still several things need to be done before merging the code into the main branch but I would open the code review now