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Fix: added missing instruction decoders and rewriters (#1280)
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@uxmal
uxmal committed Aug 30, 2023
1 parent 5f41759 commit 871c917
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Showing 29 changed files with 1,215 additions and 742 deletions.
15 changes: 9 additions & 6 deletions src/Arch/Arm/AArch64/A64Rewriter.Fpu.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -246,13 +246,16 @@ private void RewriteIntrinsicFTernary(IntrinsicProcedure intrinsic)

private void RewriteFmov()
{
if (instr.Operands[0] is VectorRegisterOperand v && v.Index >= 0)
if (instr.Operands[0] is VectorRegisterOperand v)
{
RewriteVectorElementStore(v);
}
else if (instr.Operands[1] is ImmediateOperand)
{
RewriteSimdUnaryWithScalar(fmov_intrinsic, Domain.Real);
if (v.Index >= 0)
{
RewriteVectorElementStore(v);
}
else
{
RewriteSimdUnaryWithScalar(fmov_intrinsic, Domain.Real);
}
}
else
{
Expand Down
19 changes: 13 additions & 6 deletions src/Arch/Arm/AArch64/A64Rewriter.Vector.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -24,12 +24,9 @@
using Reko.Core.Machine;
using Reko.Core.Types;
using System;
using System.Collections;
using System.Collections.Generic;
using System.Diagnostics;
using System.Linq;
using System.Text;
using System.Threading.Tasks;

namespace Reko.Arch.Arm.AArch64
{
Expand Down Expand Up @@ -356,7 +353,11 @@ private void RewriteLdN(IntrinsicProcedure intrinsic)
}
else
{
NotImplementedYet();
var args = new List<Expression> { ea };
args.Add(Constant.Int32(vec.Index));
args.AddRange(vec.GetRegisters()
.Select(r => (Expression) m.Out(r.DataType, binder.EnsureRegister(r))));
m.SideEffect(m.Fn(intrinsic.MakeInstance(64, args[1].DataType), args.ToArray()));
}
if (postIndex != null)
{
Expand All @@ -379,14 +380,20 @@ private void RewriteMla(IntrinsicProcedure intrinsic, IntrinsicProcedure intrins
if (instr.Operands[^1] is VectorRegisterOperand vr && vr.Index >= 0)
{
var dtSrc = this.MakeArrayType(instr.Operands[1]);
m.Assign(RewriteOp(0), m.Fn(intrinsicByElement.MakeInstance(dtSrc, dtSrc.ElementType),
m.Assign(RewriteOp(0), m.Fn(
intrinsicByElement.MakeInstance(dtSrc, dtSrc.ElementType),
RewriteOp(0),
RewriteOp(1),
RewriteOp(2)));
}
else
{
EmitUnitTest(" mla vector");
var dtSrc = this.MakeArrayType(instr.Operands[1]);
m.Assign(RewriteOp(0), m.Fn(
intrinsic.MakeInstance(dtSrc),
RewriteOp(0),
RewriteOp(1),
RewriteOp(2)));
}
}

Expand Down
72 changes: 39 additions & 33 deletions src/Arch/Arm/AArch64/A64Rewriter.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -172,8 +172,11 @@ public IEnumerator<RtlInstructionCluster> GetEnumerator()
case Mnemonic.ld1: RewriteLdN(ld1_intrinsic); break;
case Mnemonic.ld1r: RewriteLdNr(ld1r_intrinsic); break;
case Mnemonic.ld2: RewriteLdN(ld2_intrinsic); break;
case Mnemonic.ld2r: RewriteLdN(ld2r_intrinsic); break;
case Mnemonic.ld3: RewriteLdN(ld3_intrinsic); break;
case Mnemonic.ld3r: RewriteLdN(ld3r_intrinsic); break;
case Mnemonic.ld4: RewriteLdN(ld4_intrinsic); break;
case Mnemonic.ld4r: RewriteLdN(ld4r_intrinsic); break;
case Mnemonic.ldnp: RewriteLoadStorePair(true); break;
case Mnemonic.ldp: RewriteLoadStorePair(true); break;
case Mnemonic.ldarh: RewriteLoadAcquire(load_acquire_intrinsic, PrimitiveType.Word16); break;
Expand Down Expand Up @@ -702,34 +705,43 @@ private record IntrinsicPair(
private static readonly IntrinsicProcedure ld1_intrinsic = IntrinsicBuilder.Pure("__ld1")
.GenericTypes("T")
.PtrParam("T")
.OutParam("T")
.Variadic()
.Void();
private static readonly IntrinsicProcedure ld1r_intrinsic = IntrinsicBuilder.Pure("__ld1r")
.GenericTypes("T")
.PtrParam("T")
.OutParam("T")
.Variadic()
.Void();
private static readonly IntrinsicProcedure ld2_intrinsic = IntrinsicBuilder.Pure("__ld2")
.GenericTypes("T")
.PtrParam("T")
.OutParam("T")
.OutParam("T")
.Variadic()
.Void();
private static readonly IntrinsicProcedure ld2r_intrinsic = IntrinsicBuilder.Pure("__ld2r")
.GenericTypes("T")
.PtrParam("T")
.Variadic()
.Void();
private static readonly IntrinsicProcedure ld3_intrinsic = IntrinsicBuilder.Pure("__ld3")
.GenericTypes("T")
.PtrParam("T")
.OutParam("T")
.OutParam("T")
.OutParam("T")
.Void();
.GenericTypes("T")
.PtrParam("T")
.Variadic()
.Void();
private static readonly IntrinsicProcedure ld3r_intrinsic = IntrinsicBuilder.Pure("__ld3r")
.GenericTypes("T")
.PtrParam("T")
.Variadic()
.Void();
private static readonly IntrinsicProcedure ld4_intrinsic = IntrinsicBuilder.Pure("__ld4")
.GenericTypes("T")
.PtrParam("T")
.OutParam("T")
.OutParam("T")
.OutParam("T")
.OutParam("T")
.Void();
.GenericTypes("T")
.PtrParam("T")
.Variadic()
.Void();
private static readonly IntrinsicProcedure ld4r_intrinsic = IntrinsicBuilder.Pure("__ld4r")
.GenericTypes("T")
.PtrParam("T")
.Variadic()
.Void();
private static readonly IntrinsicProcedure load_acquire_intrinsic = new IntrinsicBuilder("__load_acquire", true)
.GenericTypes("T")
.PtrParam("T")
Expand Down Expand Up @@ -981,29 +993,23 @@ private record IntrinsicPair(
private static readonly IntrinsicProcedure st1_intrinsic = IntrinsicBuilder.Pure("__st1")
.GenericTypes("T")
.PtrParam("T")
.Param("T")
.Variadic()
.Void();
private static readonly IntrinsicProcedure st2_intrinsic = IntrinsicBuilder.Pure("__st2")
.GenericTypes("T")
.PtrParam("T")
.Param("T")
.Param("T")
.Variadic()
.Void();
private static readonly IntrinsicProcedure st3_intrinsic = IntrinsicBuilder.Pure("__st3")
.GenericTypes("T")
.PtrParam("T")
.Param("T")
.Param("T")
.Param("T")
.Void();
.GenericTypes("T")
.PtrParam("T")
.Variadic()
.Void();
private static readonly IntrinsicProcedure st4_intrinsic = IntrinsicBuilder.Pure("__st4")
.GenericTypes("T")
.PtrParam("T")
.Param("T")
.Param("T")
.Param("T")
.Param("T")
.Void();
.GenericTypes("T")
.PtrParam("T")
.Variadic()
.Void();
private static readonly IntrinsicProcedure stlr_intrinsic = new IntrinsicBuilder("__store_release", true)
.GenericTypes("T")
.PtrParam("T")
Expand Down
66 changes: 36 additions & 30 deletions src/Arch/Arm/AArch64/AArch64Disassembler.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -2484,36 +2484,30 @@ static AArch64Disassembler()
Instr(Mnemonic.st1, q30, Vmr(0, 5, 1, BHSD, 10), Mbq(5, 5)),

Instr(Mnemonic.st2, q30, Vmr(0, 5, 2, BHSD, 10), Mbq(5, 5)),
Nyi("AdvancedSimdLdStMultiple L:opcode=0:1001"),
Nyi("AdvancedSimdLdStMultiple L:opcode=0:1010"),
Nyi("AdvancedSimdLdStMultiple L:opcode=0:1011"),

Nyi("AdvancedSimdLdStMultiple L:opcode=0:1100"),
Nyi("AdvancedSimdLdStMultiple L:opcode=0:1101"),
Nyi("AdvancedSimdLdStMultiple L:opcode=0:1110"),
Nyi("AdvancedSimdLdStMultiple L:opcode=0:1111"),
Mask(30, 1,
Instr(Mnemonic.ld4, Vmr(0, 5, 4, BHSD, 10), Mb(w64, 5, 5)),
Instr(Mnemonic.ld4, Vmr(0, 5, 4, BHSD, 10), Mb(w128, 5, 5))),
invalid,
Instr(Mnemonic.st1, q30, Vmr(0, 5, 2, BHSD, 10), Mbq(5, 5)),
invalid,

invalid,
invalid,
invalid,
invalid,

Instr(Mnemonic.ld4, q30, Vmr(0, 5, 4, BHSD, 10), Mbq(5, 5)),
Nyi("AdvancedSimdLdStMultiple L:opcode=1:0001"),
Nyi("AdvancedSimdLdStMultiple L:opcode=1:0010"),
Instr(Mnemonic.ld1, q30, Vmr(0, 5, 4, BHSD, 10), Mbq(5, 5)),
Nyi("AdvancedSimdLdStMultiple L:opcode=1:0011"),
Mask(30, 1,
Instr(Mnemonic.ld3, Vmr(0, 5, 3, BHSD, 10), Mb(w64, 5, 5)),
Instr(Mnemonic.ld3, Vmr(0, 5, 3, BHSD, 10), Mb(w128, 5, 5))),

Instr(Mnemonic.ld3, q30, Vmr(0, 5, 3, BHSD, 10), Mbq(5, 5)),
Nyi("AdvancedSimdLdStMultiple L:opcode=1:0101"),
Nyi("AdvancedSimdLdStMultiple L:opcode=1:0110"),
Mask(30, 1,
Instr(Mnemonic.ld1, q30, Vmr(0, 5, 1, BHSD, 10), Mb(w64, 5, 5)),
Instr(Mnemonic.ld1, q30, Vmr(0, 5, 1, BHSD, 10), Mb(w128, 5, 5))),
Mask(30, 1,
Instr(Mnemonic.ld2, Vmr(0, 5, 2, BHSD, 10), Mb(w64, 5, 5)),
Instr(Mnemonic.ld2, Vmr(0, 5, 2, BHSD, 10), Mb(w128, 5, 5))),
Instr(Mnemonic.ld1, q30, Vmr(0, 5, 1, BHSD, 10), Mbq(5, 5)),

Instr(Mnemonic.ld2, q30, Vmr(0, 5, 2, BHSD, 10), Mbq(5, 5)),
Nyi("AdvancedSimdLdStMultiple L:opcode=1:1001"),
Mask(30, 1, " opcode=1:1010",
Instr(Mnemonic.ld1, q30, Vmr(0, 5, 2, BHSD, 10), Mb(w64, 5, 5)),
Instr(Mnemonic.ld1, q30, Vmr(0, 5, 2, BHSD, 10), Mb(w128, 5, 5))),
Instr(Mnemonic.ld1, q30, Vmr(0, 5, 2, BHSD, 10), Mbq(5, 5)),
Nyi("AdvancedSimdLdStMultiple L:opcode=1:1011"),

Nyi("AdvancedSimdLdStMultiple L:opcode=1:1100"),
Nyi("AdvancedSimdLdStMultiple L:opcode=1:1101"),
Nyi("AdvancedSimdLdStMultiple L:opcode=1:1110"),
Expand Down Expand Up @@ -2578,12 +2572,14 @@ static AArch64Disassembler()
}
Decoder AdvancedSimdLdStSingleStructure;
{
AdvancedSimdLdStSingleStructure = Mask(21,2, " AdvancedSimdLdStSingleStructure",
AdvancedSimdLdStSingleStructure = Mask(21,2, " Advanced SIMD load/store single structure",
Mask(13, 3, // L:R=0 0 opcode
Mask(10, 1, // L:R=0 0 opcode=010 size=x?
Instr(Mnemonic.st1, Vmrx(0,5,1,8), Mb(w64, 5,5)),
Instr(Mnemonic.st1, Vmrx(0,5,1,8), Mb(w128, 5,5))),
Nyi("AdvancedSimdLdStSingleStructure L:R=0 0 opcode=001"),
Mask(10, 1, // L:R=0 0 opcode=010 size=x?
Instr(Mnemonic.st3, Vmrx(0, 5, 3, 8), Mb(w64, 5, 5)),
Instr(Mnemonic.st3, Vmrx(0, 5, 3, 8), Mb(w128, 5, 5))),
Mask(10, 1, // L:R=0 0 opcode=010 size=x?
Instr(Mnemonic.st1, Vmrx(0,5,1,16),Mbq(5,5)),
invalid), // L:R=0 0 opcode=010 size=x1
Expand Down Expand Up @@ -2658,7 +2654,17 @@ static AArch64Disassembler()
Nyi("opcode=010"),
Nyi("opcode=011"),

Nyi("opcode=100"),
Mask(10, 3, " opcode=100",
Instr(Mnemonic.ld2, q30, Vmrx(0,5,2,32), Mbq(5, 5)),
Instr(Mnemonic.ld2, q30, Vmrx(0,5,2,64), Mbq(5, 5)),
invalid,
invalid,

Instr(Mnemonic.ld2, q30, Vmrx(0,5,2,32), Mbq(5, 5)),
invalid,
invalid,
invalid),

Mask(10, 2, " opcode=101",
Instr(Mnemonic.ld4, q30, Vmrx(0, 5, 4, 32), Mbq(5, 5)),
Mask(12, 1, " size=01",
Expand Down Expand Up @@ -2842,7 +2848,7 @@ static AArch64Disassembler()
LoadStoreExclusive,
invalid,
invalid),
Mask(23, 2, // op0 = 0 op1 = 00 op2 = 1
Mask(23, 2, " op2 = 1",
Select((16, 6), IsZero,
AdvancedSimdLdStMultiple,
invalid),
Expand All @@ -2853,7 +2859,7 @@ static AArch64Disassembler()
AdvancedSimdLdStSingleStructure,
invalid),
AdvancedSimdLdStSingleStructurePostIdx)),
Mask(23, 2, // op0 = 0, op1 = 1
Mask(23, 2, " op1=01",
LoadRegLit,
LoadRegLit,
invalid,
Expand All @@ -2863,7 +2869,7 @@ static AArch64Disassembler()
LdStRegPairPost,
LdStRegPairOffset,
LdStRegPairPre),
Mask(24, 1, // op0 = 0, op1 = 1x
Mask(24, 1, " op1=11",
Mask(21, 1, // LdSt op0 = 0, op1 = 3, op3 = 0, high bit of op4
Mask(10, 2,
LdStRegUnscaledImm,
Expand Down
3 changes: 3 additions & 0 deletions src/Arch/Arm/AArch64/VectorRegisterOperand.cs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,6 +25,9 @@

namespace Reko.Arch.Arm.AArch64
{
/// <summary>
/// Represents a vector register operand used in AArch64 SIMD instructions.
/// </summary>
public class VectorRegisterOperand : AbstractMachineOperand
{
public VectorRegisterOperand(PrimitiveType dt, RegisterStorage reg) : base(dt)
Expand Down
6 changes: 2 additions & 4 deletions src/Arch/PaRisc/PaRiscDisassembler.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -29,8 +29,6 @@
using System.Collections.Generic;
using System.Diagnostics;
using System.Linq;
using System.Text;
using System.Threading.Tasks;

namespace Reko.Arch.PaRisc
{
Expand Down Expand Up @@ -448,7 +446,7 @@ private static Mutator<PaRiscDisassembler> cf(int bitPos, int bitLen, ConditionO
Decoder.DumpMaskedInstruction(32, u, field.Mask << field.Position, "conditional field");
var iCond = field.Read(u);
var cond = conds[iCond];
if (cond == null)
if (cond is null)
return false;
d.cond = cond;
return true;
Expand Down Expand Up @@ -1836,7 +1834,7 @@ static PaRiscDisassembler()
invalid,

// 30
Nyi(Mnemonic.bvb, ""),
Instr(Mnemonic.bb, CTD, cf16_bb_1, r6, PcRel(assemble_12, BeFields((19, 11), (31, 1))), Annul(30)),
Instr(Mnemonic.bb, CTD, cf16_bb_1, r11, bb_bitpos(), PcRel(assemble_12, BeFields((19, 11), (31, 1))), Annul(30)),
Instr(Mnemonic.movb, CTD, cf16_shext, r11,r6,PcRel(assemble_12, BeFields((19, 11), (31, 1))), Annul(30)),
Instr(Mnemonic.movib, CTD, cf16_shext, lse(11,5),r6,PcRel(assemble_12, BeFields((19, 11), (31, 1))), Annul(30)),
Expand Down
6 changes: 5 additions & 1 deletion src/Arch/X86/Mnemonic.cs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -60,7 +60,6 @@ public enum Mnemonic : ushort
blendps,
blendvpd,
blendvps,
blendw,
blsi,
blsmsk,
blsr,
Expand Down Expand Up @@ -315,6 +314,8 @@ public enum Mnemonic : ushort
jecxz,
jg,
jge,
jknz,
jkz,
jl,
jle,
jmp,
Expand Down Expand Up @@ -457,8 +458,10 @@ public enum Mnemonic : ushort
pause,
pavgb,
pavgw,
pblendd,
pblendvb,
pblendvdb,
pblendw,
pclmulqdq,
pcmpeqb,
pcmpeqd,
Expand Down Expand Up @@ -1042,6 +1045,7 @@ public enum Mnemonic : ushort
vpavgb,
vpavgw,
vpblendd,
vpblendw,
vpbroadcastb,
vpbroadcastd,
vpbroadcasti128,
Expand Down
2 changes: 1 addition & 1 deletion src/Arch/X86/X86Disassembler.0F3A.cs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -66,7 +66,7 @@ private static void Create0F3ADecoders(Decoder[] d)

d[0x0C] = new PrefixedDecoder(dec66: VexInstr(Mnemonic.blendps, Mnemonic.vblendps, Vx,Hx,Wx,Ib));
d[0x0D] = new PrefixedDecoder(dec66: VexInstr(Mnemonic.blendpd, Mnemonic.vblendpd, Vx,Hx,Wx,Ib));
d[0x0E] = new PrefixedDecoder(dec66: VexInstr(Mnemonic.blendw, Mnemonic.vblendw, Vx,Hx,Wx,Ib));
d[0x0E] = new PrefixedDecoder(dec66: VexInstr(Mnemonic.pblendw, Mnemonic.vpblendw, Vx,Hx,Wx,Ib));
d[0x0F] = new PrefixedDecoder(
dec:Instr(Mnemonic.palignr, Pq,Qq,Ib),
dec66:Instr(Mnemonic.palignr, Vx,Hx,Wx,Ib));
Expand Down
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