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Fix: RewriterTestBase
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Over 50 unit tests weren't correctly testing!
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@uxmal
uxmal committed Sep 3, 2023
1 parent a24e9fe commit 2b56adb
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Showing 23 changed files with 163 additions and 66 deletions.
6 changes: 4 additions & 2 deletions src/UnitTests/Arch/Arm/ArmRewriterTests.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -1482,7 +1482,8 @@ public void ArmRw_smlabb()
Given_UInt32s(0xE10e3b88); // smlabb lr, r8, fp, r3
AssertCode(
"0|L--|00100000(4): 2 instructions",
"1|L--|lr = CONVERT(r8, word32, int16) *s CONVERT(fp, word32, int16) + r3");
"1|L--|lr = CONVERT(r8, word32, int16) *s CONVERT(fp, word32, int16) + r3",
"2|L--|Q = cond(lr)");
}

[Test]
Expand Down Expand Up @@ -1777,7 +1778,8 @@ public void ArmRw_qdaddeq()
AssertCode(
"0|L--|00100000(4): 3 instructions",
"1|T--|if (Test(NE,Z)) branch 00100004",
"2|L--|r8 = __sat_add<int32>(r0, __sat_mul<int32>(r0, 2<i32>))");
"2|L--|r8 = __sat_add<int32>(r0, __sat_mul<int32>(r0, 2<i32>))",
"3|L--|Q = cond(r8)");
}

[Test]
Expand Down
14 changes: 9 additions & 5 deletions src/UnitTests/Arch/Arm/T32RewriterTests.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -6740,7 +6740,8 @@ public void ThumbRw_smlabb()
Given_HexString("13FB0746"); // smlabb r6, r3, r7, r4
AssertCode(
"0|L--|00100000(4): 2 instructions",
"1|L--|r6 = CONVERT(r3, word32, int16) *s CONVERT(r7, word32, int16) + r4");
"1|L--|r6 = CONVERT(r3, word32, int16) *s CONVERT(r7, word32, int16) + r4",
"2|L--|Q = cond(r6)");
}

[Test]
Expand Down Expand Up @@ -7789,7 +7790,8 @@ public void ThumbRw_smlabt()
Given_HexString("1EFB1A68"); // smlabt r8, lr, sl, r6
AssertCode(
"0|L--|00100000(4): 2 instructions",
"1|L--|r8 = CONVERT(lr, word32, int16) *s CONVERT(r10 >> 16<i32>, word32, int16) + r6");
"1|L--|r8 = CONVERT(lr, word32, int16) *s CONVERT(r10 >> 16<i32>, word32, int16) + r6",
"2|L--|Q = cond(r8)");
}

[Test]
Expand Down Expand Up @@ -8095,8 +8097,9 @@ public void ThumbRw_adds_w()
{
Given_HexString("10EB0208"); // adds.w\tr8,r0,r2
AssertCode(
"0|L--|00100000(4): 2 instructions",
"1|L--|r8 = r0 + r2");
"0|L--|00100000(4): 2 instructions",
"1|L--|r8 = r0 + r2",
"2|L--|NZCV = cond(r8)");
}

[Test]
Expand All @@ -8105,7 +8108,8 @@ public void ThumbRw_adcs_rxx()
Given_HexString("54EB3200"); // adcs.w\tr0,r4,r2,rrx
AssertCode(
"0|L--|00100000(4): 2 instructions",
"1|L--|r0 = r4 + __rcr<word32,uint32>(r2, 1<u32>, C) + C");
"1|L--|r0 = r4 + __rcr<word32,uint32>(r2, 1<u32>, C) + C",
"2|L--|NZCV = cond(r0)");
}


Expand Down
3 changes: 2 additions & 1 deletion src/UnitTests/Arch/Avr/Avr8RewriterTests.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,8 @@ public void Avr8_rw_adiw()
Given_UInt16s(0x9601); // "adiw\tr24,01"
AssertCode(
"0|L--|0100(2): 2 instructions",
"1|L--|r25_r24 = r25_r24 + 1<16>");
"1|L--|r25_r24 = r25_r24 + 1<16>",
"2|L--|SVNZC = cond(r25_r24)");
}

[Test]
Expand Down
6 changes: 4 additions & 2 deletions src/UnitTests/Arch/Blackfin/BlackfinRewriterTests.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -56,7 +56,8 @@ public void BlackfinRw_add3()
Given_HexString("8E5B");
AssertCode( // SP = SP + P1;
"0|L--|00100000(2): 2 instructions",
"1|L--|SP = SP + P1");
"1|L--|SP = SP + P1",
"2|L--|NZVC = cond(SP)");
}

[Test]
Expand Down Expand Up @@ -152,7 +153,8 @@ public void BlackfinRw_ld_pair()
AssertCode( // (FP:P0) = [SP++];
"0|L--|00100000(2): 3 instructions",
"1|L--|v4 = SP",
"2|L--|SP = SP + 4<i32>");
"2|L--|SP = SP + 4<i32>",
"3|L--|FP_SP_P5_P4_P3_P2_P1_P0 = Mem0[v4:word32]");
}

[Test]
Expand Down
28 changes: 22 additions & 6 deletions src/UnitTests/Arch/Loongson/LoongArchRewriterTests.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -832,7 +832,10 @@ public void LoongArchRw_fldgt_s()
AssertCode( // fldgt.s $f0,$r10,$r17
"0|L--|0000000000100000(4): 5 instructions",
"1|T--|if (r10 >u r17) micro_goto skip",
"2|L--|__raise_exception(0xA<32>)");
"2|L--|__raise_exception(0xA<32>)",
"3|---|skip::",
"4|L--|v6 = Mem0[r10:real32]",
"5|L--|f0 = SEQ(SLICE(f0, word32, 32), v6)");
}

[Test]
Expand All @@ -856,7 +859,8 @@ public void LoongArchRw_fldle_s()
"1|T--|if (r14 <=u r19) micro_goto skip",
"2|L--|__raise_exception(0xA<32>)",
"3|---|skip::",
"4|L--|v6 = Mem0[r14:real32]");
"4|L--|v6 = Mem0[r14:real32]",
"5|L--|f17 = SEQ(SLICE(f17, word32, 32), v6)");
}

[Test]
Expand Down Expand Up @@ -958,7 +962,8 @@ public void LoongArchRw_fmina_s()
"0|L--|0000000000100000(4): 4 instructions",
"1|L--|v4 = SLICE(f2, word32, 0)",
"2|L--|v6 = SLICE(f16, word32, 0)",
"3|L--|v8 = __fmina<real32>(v4, v6)");
"3|L--|v8 = __fmina<real32>(v4, v6)",
"4|L--|f5 = SEQ(SLICE(f5, word32, 32), v8)");
}

[Test]
Expand Down Expand Up @@ -1076,7 +1081,11 @@ public void LoongArchRw_fstle_s()
Given_HexString("855F7738");
AssertCode( // fstle.s $f5,$r28,$r23
"0|L--|0000000000100000(4): 5 instructions",
"1|L--|v4 = SLICE(f5, real32, 0)");
"1|L--|v4 = SLICE(f5, real32, 0)",
"2|T--|if (r28 <=u r23) micro_goto skip",
"3|L--|__raise_exception(0xA<32>)",
"4|---|skip::",
"5|L--|Mem0[r28:real32] = v4");
}

[Test]
Expand Down Expand Up @@ -1215,7 +1224,10 @@ public void LoongArchRw_ldgt_b()
AssertCode( // ldgt.b $r0,$r1,$r12
"0|L--|0000000000100000(4): 5 instructions",
"1|T--|if (r1 >u r12) micro_goto skip",
"2|L--|__raise_exception(0xA<32>)");
"2|L--|__raise_exception(0xA<32>)",
"3|---|skip::",
"4|L--|v6 = Mem0[r1:int8]",
"5|L--|r0 = CONVERT(v6, int8, int64)");
}

[Test]
Expand Down Expand Up @@ -1903,7 +1915,11 @@ public void LoongArchRw_stle_b()
Given_HexString("4D017E38");
AssertCode( // stle.b $r13,$r10,$r0
"0|L--|0000000000100000(4): 5 instructions",
"1|L--|v4 = SLICE(r13, byte, 0)");
"1|L--|v4 = SLICE(r13, byte, 0)",
"2|T--|if (r10 <=u r0) micro_goto skip",
"3|L--|__raise_exception(0xA<32>)",
"4|---|skip::",
"5|L--|Mem0[r10:byte] = v4");
}

[Test]
Expand Down
3 changes: 2 additions & 1 deletion src/UnitTests/Arch/M6800/M6809RewriterTests.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -281,7 +281,8 @@ public void M6809Rw_daa()
Given_HexString("19"); // daa
AssertCode(
"0|L--|0100(1): 2 instructions",
"1|L--|a = __daa(a)");
"1|L--|a = __daa(a)",
"2|L--|NZC = cond(a)");
}

[Test]
Expand Down
3 changes: 2 additions & 1 deletion src/UnitTests/Arch/M6800/M6812RewriterTests.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -184,7 +184,8 @@ public void M6812Rw_adca_immediate()
Given_HexString("8942");
AssertCode( // adca\t#$42
"0|L--|0000(2): 2 instructions",
"1|L--|a = a + 0x42<8> + C");
"1|L--|a = a + 0x42<8> + C",
"2|L--|NZVC = cond(a)");
}

[Test]
Expand Down
10 changes: 7 additions & 3 deletions src/UnitTests/Arch/M68k/RewriterTests.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -511,7 +511,9 @@ public void M68krw_or_rev()
"0|L--|00010000(4): 5 instructions",
"1|L--|v5 = Mem0[a0 + -8<i32>:word32] | d0",
"2|L--|Mem0[a0 + -8<i32>:word32] = v5",
"3|L--|ZN = cond(v5)");
"3|L--|ZN = cond(v5)",
"4|L--|C = false",
"5|L--|V = false");
}

[Test]
Expand Down Expand Up @@ -953,7 +955,8 @@ public void M68krw_movem_to_reg()
"1|L--|v4 = a7 + 48<i32>",
"2|L--|d0 = Mem0[v4:word32]",
"3|L--|v4 = v4 + 4<i32>",
"4|L--|d1 = Mem0[v4:word32]");
"4|L--|d1 = Mem0[v4:word32]",
"5|L--|v4 = v4 + 4<i32>");
}

[Test]
Expand Down Expand Up @@ -1032,7 +1035,8 @@ public void M68krw_ror_ea()
"0|L--|00010000(2): 4 instructions",
"1|L--|v4 = __ror<word32,byte>(Mem0[a4:word32], 1<8>)",
"2|L--|Mem0[a4:word32] = v4",
"3|L--|CZN = cond(v4)");
"3|L--|CZN = cond(v4)",
"4|L--|V = false");
}

[Test]
Expand Down
12 changes: 8 additions & 4 deletions src/UnitTests/Arch/MicroBlaze/MicroBlazeRewriterTests.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -82,7 +82,8 @@ public void MicroBlazeRw_addik()
{
Given_HexString("3021001C"); // addik\tr1,r1,0000001C
AssertCode(
"0|L--|00100000(4): 1 instructions");
"0|L--|00100000(4): 1 instructions",
"1|L--|r1 = r1 + 0x1C<32>");
}

[Test]
Expand Down Expand Up @@ -117,7 +118,8 @@ public void MicroBlazeRw_andi()
{
Given_HexString("A4A400FF"); // andi\tr5,r4,000000FF
AssertCode(
"0|L--|00100000(4): 1 instructions");
"0|L--|00100000(4): 1 instructions",
"1|L--|r5 = r4 & 0xFF<32>");
}

[Test]
Expand Down Expand Up @@ -406,7 +408,8 @@ public void MicroBlazeRw_rsubk()
{
Given_HexString("16A3A800"); // rsubk\tr21,r3,r21
AssertCode(
"0|L--|00100000(4): 1 instructions");
"0|L--|00100000(4): 1 instructions",
"1|L--|r21 = r21 - r3");
}

[Test]
Expand Down Expand Up @@ -521,7 +524,8 @@ public void MicroBlazeRw_xori()
{
Given_HexString("AAA3FFFF"); // xori\tr21,r3,FFFFFFFF
AssertCode(
"0|L--|00100000(4): 1 instructions");
"0|L--|00100000(4): 1 instructions",
"1|L--|r21 = r3 ^ 0xFFFFFFFF<32>");
}
}
}
3 changes: 2 additions & 1 deletion src/UnitTests/Arch/MilStd1750/MilStd1750RewriterTests.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -700,7 +700,8 @@ public void MS1750Rw_orr()
Given_HexString("E102");
AssertCode( // orr gp0,gp2
"0|L--|0100(1): 2 instructions",
"1|L--|gp0 = gp0 | gp2");
"1|L--|gp0 = gp0 | gp2",
"2|L--|PZN = cond(gp0)");
}

[Test]
Expand Down
8 changes: 6 additions & 2 deletions src/UnitTests/Arch/PaRisc/PaRiscRewriterTests.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -96,7 +96,9 @@ public void PaRiscRw_add_l_uv()
{
Given_HexString("082A9A13");
AssertCode(
"0|T--|00100000(4): 2 instructions");
"0|T--|00100000(4): 2 instructions",
"1|L--|r19 = r10 + r1",
"2|T--|if (Test(NO,r19 -u 0<64>)) branch 00100008");
}

[Test]
Expand All @@ -114,7 +116,9 @@ public void PaRiscRw_add_znv()
{
Given_HexString("0859AA0A");
AssertCode(
"0|T--|00100000(4): 2 instructions");
"0|T--|00100000(4): 2 instructions",
"1|L--|r10 = r25 + r2",
"2|T--|if (r10 != 0<64> & Test(OV,r10 - 0<64>)) branch 00100008");
}

[Test]
Expand Down
6 changes: 4 additions & 2 deletions src/UnitTests/Arch/Padauk/PDK15/PadaukRewriter_PDK15Tests.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,8 @@ public void Pdk15Rw_add_a_imm()
Given_HexString("FF50");
AssertCode( // add a,+00FF
"0|L--|0100(1): 2 instructions",
"1|L--|a = a + 0xFF<8>");
"1|L--|a = a + 0xFF<8>",
"2|L--|ZCAV = cond(a)");
}

[Test]
Expand Down Expand Up @@ -186,7 +187,8 @@ public void Pdk15Rw_or()
Given_HexString("031D");
AssertCode( // or a,[0x3]
"0|L--|0100(1): 2 instructions",
"1|L--|a = a | Mem0[0x0003<p16>:byte]");
"1|L--|a = a | Mem0[0x0003<p16>:byte]",
"2|L--|Z = cond(a)");
}

[Test]
Expand Down
3 changes: 2 additions & 1 deletion src/UnitTests/Arch/Pdp/Pdp10/Pdp10RewriterTests.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -1331,7 +1331,8 @@ public void Pdp10Rw_sosle_ac()
"1|L--|v3 = Mem0[0x024022<p18>:word36] - 1<36>",
"2|L--|Mem0[0x024022<p18>:word36] = v3",
"3|L--|r1 = v3",
"4|L--|C0C1VT = cond(v3)");
"4|L--|C0C1VT = cond(v3)",
"5|T--|if (v3 <= 0<36>) branch 200002");
}

[Test]
Expand Down
7 changes: 5 additions & 2 deletions src/UnitTests/Arch/PowerPC/PowerPcRewriterTests.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -651,7 +651,9 @@ public void PPCRw_bdnzfl()
Given_HexString("401D26CF");
AssertCode( // bdnzfl cr7+gt,$000026CC
"0|T--|00100000(4): 3 instructions",
"1|L--|ctr = ctr - 1<32>");
"1|L--|ctr = ctr - 1<32>",
"2|T--|if (ctr == 0<32> || Test(GT,cr7)) branch 00100004",
"3|T--|call 000026CC (0)");
}

[Test]
Expand Down Expand Up @@ -2733,7 +2735,8 @@ public void PPCRw_vcmpequw128()
Given_HexString("1BFFF265");
AssertCode( // vcmpequw128. v63,v63,v62
"0|L--|00100000(4): 2 instructions",
"1|L--|v63 = __vector_cmpeq<uint32[4]>(v63, v62)");
"1|L--|v63 = __vector_cmpeq<uint32[4]>(v63, v62)",
"2|L--|cr6 = cond(v63)");
}

[Test]
Expand Down
37 changes: 27 additions & 10 deletions src/UnitTests/Arch/RewriterTestBase.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,7 @@
using Reko.Core.Memory;
using Reko.Core.Rtl;
using Reko.Core.Services;
using System;
using System.ComponentModel.Design;
using System.Linq;

Expand Down Expand Up @@ -101,20 +102,36 @@ protected void AssertCode(params string[] expected)
int i = 0;
var frame = Architecture.CreateFrame();
var host = CreateRewriterHost();
var rewriter = GetRtlStream(mem, frame, host).GetEnumerator();
while (i < expected.Length && rewriter.MoveNext())
{
Assert.AreEqual(expected[i], string.Format("{0}|{1}|{2}", i, RtlInstruction.FormatClass(rewriter.Current.Class), rewriter.Current));
++i;
var ee = rewriter.Current.Instructions.OfType<RtlInstruction>().GetEnumerator();
while (i < expected.Length && ee.MoveNext())
var actual = GetRtlStream(mem, frame, host)
.SelectMany(cluster =>
{
Assert.AreEqual(expected[i], string.Format("{0}|{1}|{2}", i, RtlInstruction.FormatClass(ee.Current.Class), ee.Current));
var a = new string[cluster.Instructions.Length + 1];
a[0] = string.Format("{0}|{1}|{2}", i, RtlInstruction.FormatClass(cluster.Class), cluster);
++i;
for (int j = 0; j < cluster.Instructions.Length; ++j)
{
var instr = cluster.Instructions[j];
a[j + 1] = string.Format("{0}|{1}|{2}", i, RtlInstruction.FormatClass(instr.Class), instr);
++i;
}
return a;
}).ToArray();
try
{
var c = Math.Min(expected.Length, actual.Length);
for (i = 0; i < c; ++i)
{
Assert.AreEqual(expected[i], actual[i]);
}
Assert.AreEqual(expected.Length, actual.Length, $"Expected {expected.Length} RTL instructions but got {actual.Length}.");
}
catch
{
Console.WriteLine(string.Join(
"," + Environment.NewLine,
actual.Select(s =>$"\"{s}\"")));
throw;
}
Assert.AreEqual(expected.Length, i, $"Expected {expected.Length} RTL instructions.");
Assert.IsFalse(rewriter.MoveNext(), "More instructions were emitted than were expected.");
}
}
}
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