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verilog.c: keyword "unsigned1" should be "unsigned", without the 1 #4110

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The list of Verilog keywords fetched from Appendix B of the Verilog standard accidentally captured the footnote "1" in keyword unsigned¹:

List of keywords

... triand trior trireg unsigned¹ use uwire vectored ...

¹ unsigned is reserved for possible future usage

Fix minor typo in verilog.c: keyword "unsigned1" should be "unsigned", without the 1.
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codecov bot commented Nov 11, 2024

Codecov Report

All modified and coverable lines are covered by tests ✅

Project coverage is 85.85%. Comparing base (b6d1cac) to head (684ec80).

Additional details and impacted files
@@           Coverage Diff           @@
##           master    #4110   +/-   ##
=======================================
  Coverage   85.85%   85.85%           
=======================================
  Files         239      239           
  Lines       58629    58629           
=======================================
  Hits        50333    50333           
  Misses       8296     8296           

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LGTM

@masatake masatake assigned masatake and hirooih and unassigned masatake Nov 12, 2024
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5 participants