Skip to content

Commit

Permalink
make STANDALONE work
Browse files Browse the repository at this point in the history
  • Loading branch information
ansaschmulbach committed Aug 2, 2024
1 parent 4a0784d commit f39e2ad
Show file tree
Hide file tree
Showing 4 changed files with 110 additions and 50 deletions.
7 changes: 3 additions & 4 deletions src/main/scala/logphy/LinkTrainingFSM.scala
Original file line number Diff line number Diff line change
Expand Up @@ -61,9 +61,7 @@ class LinkTrainingFSM(
val rdiBringupIO = new RdiBringupIO
}
val trainingOperationIO =
Input(
new TrainingOperation(afeParams, linkTrainingParams.maxPatternCount),
)
new TrainingOperation(afeParams, linkTrainingParams.maxPatternCount)
val currentState = Output(LinkTrainingState())
})

Expand Down Expand Up @@ -363,7 +361,8 @@ class LinkTrainingFSM(
nextState := Mux(
mbInit.io.error,
LinkTrainingState.linkError,
LinkTrainingState.mbTrain,
if (afeParams.STANDALONE) { LinkTrainingState.linkInit }
else { LinkTrainingState.mbTrain },
)
}
}
Expand Down
4 changes: 3 additions & 1 deletion src/main/scala/logphy/LogicalPhy.scala
Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,9 @@ class LogicalPhy(
)
}

/** TODO: replace this with MMIO module instantiations */
trainingModule.io.trainingOperationIO := DontCare

if (afeParams.STANDALONE) {
trainingModule.io.mainbandFSMIO.pllLock <> io.mbAfe.get.pllLock
} else { trainingModule.io.mainbandFSMIO.pllLock := 0.U }
Expand Down Expand Up @@ -82,7 +85,6 @@ class LogicalPhy(
lanes.io.scramble := true.B

/** Connect internal FIFO to AFE */

if (afeParams.STANDALONE) {
lanes.io.mainbandLaneIO.txData <> io.mbAfe.get.txData
lanes.io.mainbandLaneIO.rxData <> io.mbAfe.get.rxData
Expand Down
9 changes: 4 additions & 5 deletions src/test/scala/logphy/LinkTrainingFSMTest.scala
Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@ class LinkTrainingFSMTest extends AnyFlatSpec with ChiselScalatestTester {
println("Successfully initialized sideband")
initMB(c)
println("Successfully initialized mainband")
trainMB(c)
// trainMB(c)
println("Successfully trained mainband")

c.io.currentState.expect(LinkTrainingState.linkInit)
Expand Down Expand Up @@ -109,10 +109,9 @@ class LinkTrainingFSMTest extends AnyFlatSpec with ChiselScalatestTester {
c.clock.step(3)
}

private def trainMB(c: LinkTrainingFSM): Unit = {
c.io.currentState.expect(LinkTrainingState.mbTrain)

}
// private def trainMB(c: LinkTrainingFSM): Unit = {
// c.io.currentState.expect(LinkTrainingState.mbTrain)
// }

private def testTransitionOutOfReset(c: LinkTrainingFSM): Unit = {
c.io.currentState.expect(LinkTrainingState.reset)
Expand Down
140 changes: 100 additions & 40 deletions src/test/scala/logphy/MBTrainerTest.scala
Original file line number Diff line number Diff line change
Expand Up @@ -25,11 +25,17 @@ class MBTrainerTest extends AnyFlatSpec with ChiselScalatestTester {
linkTrainingParams.sbClockFreqAnalog / afeParams.sbSerializerRatio
val timeoutCyclesDefault = (0.008 * sbClockFreq).toInt
var patternUICount = afeParams.mbLanes * afeParams.mbSerializerRatio * 4
val maxErrors = 0

initialExpectedValues(c)
triggerOperation(c, transmitPattern, patternUICount)
triggerOperation(
c,
transmitPattern,
patternUICount,
timeoutCyclesDefault,
maxErrors,
)

val maxErrors = 0
var errorCount = Vec.Lit(
Seq.fill(afeParams.mbLanes)(1.U(maxPatternCountWidth.W)): _*,
)
Expand All @@ -38,7 +44,6 @@ class MBTrainerTest extends AnyFlatSpec with ChiselScalatestTester {
transmitPattern,
timeoutCyclesDefault,
patternUICount,
maxErrors,
errorCount,
)

Expand All @@ -48,17 +53,23 @@ class MBTrainerTest extends AnyFlatSpec with ChiselScalatestTester {
Seq.tabulate(afeParams.mbLanes)(x => x.U(maxPatternCountWidth.W)): _*,
)

triggerOperation(c, transmitPattern, patternUICount)
triggerOperation(
c,
transmitPattern,
patternUICount,
timeoutCyclesDefault,
maxErrors,
)

completeTrainingOperation(
c,
transmitPattern,
timeoutCyclesDefault,
patternUICount,
maxErrors,
errorCount,
)

triggerExit(c, timeoutCyclesDefault)
exitTraining(c, timeoutCyclesDefault)

}
Expand All @@ -71,20 +82,28 @@ class MBTrainerTest extends AnyFlatSpec with ChiselScalatestTester {
linkTrainingParams.sbClockFreqAnalog / afeParams.sbSerializerRatio
val timeoutCyclesDefault = (0.008 * sbClockFreq).toInt
var patternUICount = afeParams.mbLanes * afeParams.mbSerializerRatio * 4
val maxErrors = 0

initialExpectedValues(c)
triggerOperation(c, transmitPattern, patternUICount)

val maxErrors = 0
/** Trigger operation via sideband */
triggerOperationSB(
c,
timeoutCyclesDefault,
transmitPattern,
patternUICount,
maxErrors,
)

var errorCount = Vec.Lit(
Seq.fill(afeParams.mbLanes)(1.U(maxPatternCountWidth.W)): _*,
)

completeTrainingOperation(
c,
transmitPattern,
timeoutCyclesDefault,
patternUICount,
maxErrors,
errorCount,
)

Expand All @@ -94,22 +113,65 @@ class MBTrainerTest extends AnyFlatSpec with ChiselScalatestTester {
Seq.tabulate(afeParams.mbLanes)(x => x.U(maxPatternCountWidth.W)): _*,
)

triggerOperation(c, transmitPattern, patternUICount)
/** NOTE: cannot re-trigger operation with sideband as sideband is not
* expecting a begin training request
*/
triggerOperation(
c,
transmitPattern,
patternUICount,
timeoutCyclesDefault,
maxErrors,
)

completeTrainingOperation(
c,
transmitPattern,
timeoutCyclesDefault,
patternUICount,
maxErrors,
errorCount,
)

/** Trigger exit via sideband */
triggerExitSB(c, timeoutCyclesDefault)

exitTraining(c, timeoutCyclesDefault)

}
}

private def triggerExitSB(c: MBTrainer, timeoutCyclesDefault: Int): Unit = {

expectSBReq(
c = c,
bitPat = SBM.MBTRAIN_END_TX_INIT_D_TO_C_POINT_TEST_REQ,
MessageRequestType.RECEIVE,
timeoutCyclesDefault,
msgInfo = 0,
data = 0,
)
sbMsgSuccess(c)
}

private def triggerOperationSB(
c: MBTrainer,
timeoutCyclesDefault: Int,
transmitPattern: TransmitPattern.Type,
patternUICount: Int,
maxErrors: Int,
): Unit = {
val data = 0 | transmitPattern.litValue | (BigInt(patternUICount) << 43)
expectSBReq(
c,
SBM.MBTRAIN_START_TX_INIT_D_TO_C_POINT_TEST_REQ,
MessageRequestType.RECEIVE,
timeoutCyclesDefault,
msgInfo = 0,
data = 0,
)
sbMsgSuccess(c, data)
}

private def initialExpectedValues(c: MBTrainer): Unit = {
c.io.patternGeneratorIO.transmitReq.expectInvalid()
c.io.patternGeneratorIO.resp.ready.expect(false.B)
Expand All @@ -123,21 +185,6 @@ class MBTrainerTest extends AnyFlatSpec with ChiselScalatestTester {

private def exitTraining(c: MBTrainer, timeoutCyclesDefault: Int): Unit = {

/** Trigger exit */
triggerExit(c)

/** Expect Pt Test End Test Req */
expectSBReq(
c = c,
bitPat = SBM.MBTRAIN_END_TX_INIT_D_TO_C_POINT_TEST_REQ,
reqType = MessageRequestType.SEND,
timeoutCyclesDefault = timeoutCyclesDefault,
msgInfo = 0,
data = 0,
)

sbMsgSuccess(c)

expectSBReq(
c = c,
bitPat = SBM.MBTRAIN_END_TX_INIT_D_TO_C_POINT_TEST_RESP,
Expand All @@ -154,16 +201,30 @@ class MBTrainerTest extends AnyFlatSpec with ChiselScalatestTester {
c.io.err.expect(false.B)
}

private def triggerExit(c: MBTrainer): Unit = {
private def triggerExit(c: MBTrainer, timeoutCyclesDefault: Int): Unit = {
c.io.trainingOperationIO.triggerExit.poke(true.B)
c.clock.step()
c.io.trainingOperationIO.triggerExit.poke(false.B)

/** Expect Pt Test End Test Req */
expectSBReq(
c = c,
bitPat = SBM.MBTRAIN_END_TX_INIT_D_TO_C_POINT_TEST_REQ,
reqType = MessageRequestType.SEND,
timeoutCyclesDefault = timeoutCyclesDefault,
msgInfo = 0,
data = 0,
)

sbMsgSuccess(c)
}

private def triggerOperation(
c: MBTrainer,
transmitPattern: TransmitPattern.Type,
patternUICount: Int,
timeoutCyclesDefault: Int,
maxErrors: Int,
): Unit = {
c.io.trainingOperationIO.triggerNew.poke(true.B)
c.io.trainingOperationIO.pattern.poke(transmitPattern)
Expand All @@ -174,18 +235,6 @@ class MBTrainerTest extends AnyFlatSpec with ChiselScalatestTester {
c.io.patternGeneratorIO.transmitReq.expectInvalid()
c.io.patternGeneratorIO.resp.ready.expect(false.B)
println("External trigger")
}

private def completeTrainingOperation(
c: MBTrainer,
transmitPattern: TransmitPattern.Type,
timeoutCyclesDefault: Int,
patternUICount: Int,
maxErrors: Int,
errorCount: Vec[UInt],
): Unit = {

println("********** BEGIN TRAINING OPERATION ***********")

val data = 0 | transmitPattern.litValue | (BigInt(patternUICount) << 43)
expectSBReq(
Expand All @@ -200,6 +249,17 @@ class MBTrainerTest extends AnyFlatSpec with ChiselScalatestTester {

/** Complete PTTest SB request */
sbMsgSuccess(c)
}

private def completeTrainingOperation(
c: MBTrainer,
transmitPattern: TransmitPattern.Type,
timeoutCyclesDefault: Int,
patternUICount: Int,
errorCount: Vec[UInt],
): Unit = {

println("********** BEGIN TRAINING OPERATION ***********")

/** Expect PTTest SB response */
expectSBReq(
Expand Down Expand Up @@ -313,10 +373,10 @@ class MBTrainerTest extends AnyFlatSpec with ChiselScalatestTester {
c.io.patternGeneratorIO.resp.ready.expect(false.B)
}

private def sbMsgSuccess(c: MBTrainer): Unit = {
private def sbMsgSuccess(c: MBTrainer, data: BigInt = 0): Unit = {
c.io.sbTrainIO.msgReqStatus.enqueueNow(
(new MessageRequestStatus).Lit(
_.data -> 0.U,
_.data -> data.U,
_.status -> MessageRequestStatusType.SUCCESS,
),
)
Expand Down

0 comments on commit f39e2ad

Please sign in to comment.