This is a port of the digital side of OsciBear on Arty 35T. In theory it should also work for Arty 100T without any modifications. Not the most elegant code and I don't know what I'm doing sometimes but it works.
Key Functionality:
✓ AES accelerator
⨯ BLE Baseband
✓ DMA
✓ 1 Custom-sized Rocket core
✓ Adjustable to very slow clock
Periphery:
✓ JTAG (GDB)
✓ UART
✓ GPIO x3
✓ QSPI
✓ 1-bit Serial Tilelink
In addition to following the regular chipyard set up process, a couple of extra submodules needs to be added (if they are not already set up). Notably:
https://github.com/ucberkeley-ee290c/sp21-aes-rocc-accelforgenerators/aeshttps://github.com:ucberkeley-ee290c/sp21-ble-basebandforgenerators/baseband(although I think for now this is commented out so probably don't need this)https://github.com/ucberkeley-ee290c/sp21-dmaforgenerators/dma
Once chipyard, the submodules and Vivado has been set-up properly, run the following command under the fpga directory:
make bitstream SUB_PROJECT=arty-osci
Two pre-generated bitstreams are located here.
To aid debugging high speed interfaces like TileLink, the current version generates a bitstream with a very slow clock. This is done through modifying two files.
Modifications for this file has NOT been uploaded since it's a different submodule and I didn't want to make a separate repo for a 2 line change. But this mostly concerns outputting a slow clock through Xilinx's clock wizard. I changed CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {65.000} to CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {4.687}, making the built-in divider output a 4.687 MHz signal. This is not strictly necessary as the second file outlines.
Oftentimes even a 4 MHz clock isn't slow enough as is the case when probing signals with jumper wires connected in serial. This is remedied through manually instatiating a clock divider in the TestHarness. Simply change the divider width and divisor to fine tune the output frequency.
Note that I'm doing a divide by 32 on the 4.687 MHz signal, giving a 146.5 KHz clock period.
The pinouts are found in the HarnessBinders.scala file.
For quick reference, JTAG:
TCK = jd_2
TMS = jd_5
TDI = jd_4
TDO = jd_0
SRSTn = jd_6
- Test the accelerator and the DMA
Email [email protected] or find me on the BAR Slack.
- Stable Documentation: https://chipyard.readthedocs.io/
- User Question Forum: https://groups.google.com/forum/#!forum/chipyard
- Bugs and Feature Requests: https://github.com/ucb-bar/chipyard/issues
To get started using Chipyard, see the stable documentation on the Chipyard documentation site: https://chipyard.readthedocs.io/
Chipyard is an open source framework for agile development of Chisel-based systems-on-chip. It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other Berkeley projects to produce a RISC-V SoC with everything from MMIO-mapped peripherals to custom accelerators. Chipyard contains processor cores (Rocket, BOOM, CVA6 (Ariane)), accelerators (Hwacha, Gemmini, NVDLA), memory systems, and additional peripherals and tooling to help create a full featured SoC. Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation (FireSim), automated VLSI flows (Hammer), and software workload generation for bare-metal and Linux-based systems (FireMarshal). Chipyard is actively developed in the Berkeley Architecture Research Group in the Electrical Engineering and Computer Sciences Department at the University of California, Berkeley.
- Chipyard Stable Documentation: https://chipyard.readthedocs.io/
- Chipyard (x FireSim) Tutorial: https://fires.im/tutorial
- Chipyard Basics slides: https://fires.im/isca22-slides-pdf/02_chipyard_basics.pdf
- Chipyard Tutorial Exercise slides: https://fires.im/isca22-slides-pdf/03_building_custom_socs.pdf
- Join the Chipyard Mailing List: https://groups.google.com/forum/#!forum/chipyard
- If you find a bug or would like propose a feature, post an issue on this repo: https://github.com/ucb-bar/chipyard/issues
- See CONTRIBUTING.md
If used for research, please cite Chipyard by the following publication:
@article{chipyard,
author={Amid, Alon and Biancolin, David and Gonzalez, Abraham and Grubb, Daniel and Karandikar, Sagar and Liew, Harrison and Magyar, Albert and Mao, Howard and Ou, Albert and Pemberton, Nathan and Rigge, Paul and Schmidt, Colin and Wright, John and Zhao, Jerry and Shao, Yakun Sophia and Asanovi\'{c}, Krste and Nikoli\'{c}, Borivoje},
journal={IEEE Micro},
title={Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs},
year={2020},
volume={40},
number={4},
pages={10-21},
doi={10.1109/MM.2020.2996616},
ISSN={1937-4143},
}
- Chipyard
These additional publications cover many of the internal components used in Chipyard. However, for the most up-to-date details, users should refer to the Chipyard docs.
- Generators
- Sims
- Tools
- VLSI
- Hammer: E. Wang, et al., ISQED'20. PDF.
This work is supported by the NSF CCRI ENS Chipyard Award #201662.