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15 Open 14 Closed
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Issues list

Remove dependency on sifive-blocks
#156 opened Jan 18, 2023 by jerryz123
1
It cannot compatible 128 bit data length
#147 opened Jul 11, 2022 by matchchen
2
Make BlockDevice base address come from Config
#131 opened Apr 16, 2021 by timsnyder-siv
1
Make SimDRAM work when physical address width > 32 bits. bug
#127 opened Mar 29, 2021 by jerryz123
TSI Host Widget Full Integration Test enhancement help wanted
#117 opened Jan 8, 2021 by abejgonzalez
TSI Host Widget Documentation enhancement help wanted
#116 opened Jan 8, 2021 by abejgonzalez
value += is not a member of String
#95 opened Jul 23, 2020 by apaj
SerialAdapter should require minLatency > 0
#88 opened Jun 13, 2020 by mwachs5
2
Use PlusArgArtefacts.append to avoid emulator.cc hacks in next RC bump
#86 opened May 21, 2020 by jwright6323
Eventually move to the InModuleBody paradigm instead of ModuleImps to mirror rocket-chip
#77 opened Apr 16, 2020 by jwright6323
Import issue: compile fails, can't find UARTPortIO
#72 opened Mar 24, 2020 by bradley-evans
Provide parameterization of SERIAL_IF_WIDTH
#63 opened Jan 18, 2020 by jerryz123
Bidirectional serdes safe usage
#49 opened Jul 12, 2019 by colinschmidt
2
ClockUtil unit tests
#40 opened Mar 28, 2019 by jwright6323
Making Host/Target coordination for the TLSerdesser easier enhancement
#37 opened Mar 5, 2019 by jwright6323
@jwright6323
2
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