Extending Torture with RISC-V Vector ext. (v0.9)

README

@@ -258,3 +258,97 @@ Future TODO
  - code refactoring
    + consolidate RegPool logic
    + detect and suppress unallocatable sequences
+
+###########################################################################
+Extending Torture for RISC-V Vector ext. (v0.9)
+###########################################################################
+
+---------------------------------------------------------------------------
+Organization and Members
+---------------------------------------------------------------------------
+# Organization: Lampro Mellon
+# Date: August 17th, 2020
+# Members:
+        Hassaan Khalid
+        Nouman Akbar
+        Usman Qadir
+        Faisal Saeed
+        Faisal Usman
+        Dr. Faisal Iqbal
+
+---------------------------------------------------------------------------
+New Instructions
+---------------------------------------------------------------------------
+$ git clone <repo-https-link>
+$ cd <repo-name>
+$ git submodule update --init
+$ sudo apt-get install -y device-tree-compiler
+$ ./build_rvv09_toolchain.sh
+
+# CLOSE terminal and open a new one in Torture directory:
+
+$ sbt
+
+# Wait for sbt to import libraries and then type "exit" in it's CLI
+# Torture is all set up now and above commands don't need to be run again
+
+# Generate a test and simulate it on Spike:
+
+$ make igentest
+
+---------------------------------------------------------------------------
+Overview of changes
+---------------------------------------------------------------------------
+# Added RISC-V vector registers (v0 - v31)
+# Added RISC-V vector instruction opcodes
+# Added RISC-V vector instructions sequence generator (SeqRVV.scala)
+# Added new random functions for generating vector instructions
+# Added RISC-V vector opcode usage section in stats file
+# Added RISC-V vector register accesses section in stats file
+# Added ISA coverage section in stats file
+# Added knobs for customizing vector tests in config file
+# Added preset config files for RISC-V vector testing
+# Bumped up commit of riscv-test-env ("env" folder)
+# Added script for building vector (v0.9) enabled RISC-V toolchain
+# Added config_README file
+
+---------------------------------------------------------------------------
+Configuring RISC-V vector instructions for Torture tests
+---------------------------------------------------------------------------
+To configure or customize the vector instructions, the same default.config
+file will be used. See the config_README file in the config folder to
+understand what each option does.
+
+---------------------------------------------------------------------------
+Required RISC-V tools
+---------------------------------------------------------------------------
+The vector extension compatible RISC-V tools are necessary for use with
+this version of the Torture test generator. The script
+"build_rvv09_toolchain.sh" is provided to build them.
+
+Note:
+1. env folder contains the repo: https://github.com/riscv/riscv-test-env
+   This repo was updated to the Nov 24th, 2020 commit which had the
+   relavant header files for vector instructions.
+   {commit hash: 1d9e7eaa85d9929d3f76b460c25ca26e1245a371}
+
+2. Spike has to be used with an old commit as newer ones are modified for
+   v1.0 of the vector extension. For v0.9, the July 15th, 2020 commit is
+   used.
+   {commit hash: 759f4eba829d299eb34cd1568d3f4694e0d198cb}
+
+---------------------------------------------------------------------------
+Spike "signature mismatch" issue
+---------------------------------------------------------------------------
+There is a "Spike signature mismatch" error that occurs spontaneously with
+the "igentest" command. It is concluded that this is a bug in Spike
+simulator, as this error does not occur with the vector v1.0 updates of
+the same tool.
+
+---------------------------------------------------------------------------
+Future TO-DO
+---------------------------------------------------------------------------
+# Make the Torture’s vector extension compatible for v1.0
+# Add support for Zvqmac and Zvediv extensions
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------

build_rvv09_toolchain.sh

@@ -0,0 +1,59 @@
+#!/usr/bin/env bash
+
+# exit script if any command fails
+set -e
+set -o pipefail
+
+# Check that git version is at least 1.7.8
+MYGIT=$(git --version)
+MYGIT=${MYGIT#'git version '} # Strip prefix
+case ${MYGIT} in
+[1-9]*) ;;
+*) echo 'warning: unknown git version' ;;
+esac
+MINGIT="1.7.8"
+if [ "$MINGIT" != "$(echo -e "$MINGIT\n$MYGIT" | sort -V | head -n1)" ]; then
+  echo "This script requires git version $MINGIT or greater. Exiting."
+  false
+fi
+
+# Make new directory for toolchain in home
+cd $HOME
+mkdir rvv09
+cd rvv09
+
+# Setup Spike simulator
+git clone https://github.com/riscv/riscv-isa-sim.git
+cd riscv-isa-sim
+git checkout 759f4eba829d299eb34cd1568d3f4694e0d198cb
+mkdir build
+cd build
+../configure --prefix=$HOME/rvv09/rvv09-tools/spike
+make
+make install
+cd ../..
+
+# Setup RISC-V GNU toolchain
+git clone https://github.com/riscv/riscv-gnu-toolchain.git --branch rvv-0.9.x --single-branch riscv-gnu-toolchain_rvv-0.9.x
+cd riscv-gnu-toolchain_rvv-0.9.x
+git submodule update --init --recursive riscv-binutils riscv-gcc riscv-glibc riscv-dejagnu riscv-newlib riscv-gdb
+mkdir build
+cd build
+../configure --prefix=$HOME/rvv09/rvv09-tools/gnu --enable-multilib
+make
+make install
+cd ../..
+
+# Setup Proxy Kernel
+git clone https://github.com/riscv/riscv-pk.git
+cd riscv-pk
+mkdir build
+cd build
+PATH=$HOME/rvv09/rvv09-tools/gnu/bin:$PATH ../configure --prefix=$HOME/rvv09/rvv09-tools/pk --host=riscv64-unknown-elf
+PATH=$HOME/rvv09/rvv09-tools/gnu/bin:$PATH make
+PATH=$HOME/rvv09/rvv09-tools/gnu/bin:$PATH make install
+cd ../..
+
+# Set path and RISC-V environment variables in .bashrc
+echo 'export RISCV=$HOME/rvv09/rvv09-tools/gnu' >> ~/.bashrc
+echo 'export PATH=$HOME/rvv09/rvv09-tools/gnu/bin:$HOME/rvv09/rvv09-tools/gnu/riscv64-unknown-elf/bin:$HOME/rvv09/rvv09-tools/spike/bin:$HOME/rvv09/rvv09-tools/pk/riscv64-unknown-elf/bin:$PATH' >> ~/.bashrc

config/config_README

@@ -0,0 +1,79 @@
+torture.generator.nseqs           3000  # number of instructions in program segment
+torture.generator.memsize         8192  # size of memory; to be used by integer, floating-point and vector registers
+torture.generator.fprnd           0     # *{unused parameter}
+torture.generator.amo             true  # scalar atomic instructions flag
+torture.generator.mul             true  # scalar multiplication instructions flag
+torture.generator.divider         true  # scalar division instructions flag
+torture.generator.segment         true  # Enables consecutive instruction sequences; default => true
+torture.generator.loop            true  # enable loop for running program segment multiple times
+torture.generator.loop_size       64    # number of times to rerun program segment
+
+torture.generator.mix.xmem        5     # scalar integer memory instructions percentage
+torture.generator.mix.xbranch     5     # scalar integer branch instructions percentage
+torture.generator.mix.xalu        10    # scalar integer ALU instructions percentage
+torture.generator.mix.fgen        20    # scalar floating-point ALU instructions percentage
+torture.generator.mix.fpmem       10    # scalar floating-point memory instructions percentage
+torture.generator.mix.fax         10    # scalar floating-point comparison/conversion instructions percentage
+torture.generator.mix.fdiv        10    # scalar floating-point division instructions percentage
+torture.generator.mix.vec         0     # Hwacha vector instructions percentage
+torture.generator.mix.rvv         30    # RISC-V vector (v0.9) instructions percentage
+
+torture.generator.vec.vf          1
+torture.generator.vec.seq         10
+torture.generator.vec.memsize     128
+torture.generator.vec.numsregs    64
+torture.generator.vec.mul         false
+torture.generator.vec.div         false
+torture.generator.vec.mix         true
+torture.generator.vec.fpu         false
+torture.generator.vec.fma         false
+torture.generator.vec.fcvt        false
+torture.generator.vec.fdiv        false
+torture.generator.vec.amo         false
+torture.generator.vec.seg         false
+torture.generator.vec.stride      false
+torture.generator.vec.pred_alu    true
+torture.generator.vec.pred_mem    true
+
+torture.generator.vec.mix.valu    20
+torture.generator.vec.mix.vpop    60
+torture.generator.vec.mix.vmem    20
+torture.generator.vec.mix.vonly   0
+
+torture.generator.rvv.vmem_unit   true  # RISC-V vector (v0.9) memory (unit-stride) instructions flag
+torture.generator.rvv.vmem_const  true  # RISC-V vector (v0.9) memory (constant-stride) instructions flag
+torture.generator.rvv.vmem_vect   true  # RISC-V vector (v0.9) memory (indexed-stride) instructions flag
+torture.generator.rvv.Zvlsseg     false # RISC-V vector (v0.9) segmented memory instructions flag *(unsupported on Spike)
+torture.generator.rvv.Zvamo       false # RISC-V vector (v0.9) atomic instructions flag *(unsupported on Spike)
+torture.generator.rvv.vfloat      true  # RISC-V vector (v0.9) floating-point instructions flag
+torture.generator.rvv.vinteger    true  # RISC-V vector (v0.9) integer instructions flag
+torture.generator.rvv.vfixed      true  # RISC-V vector (v0.9) fixed-point instructions flag
+torture.generator.rvv.vreduce     true  # RISC-V vector (v0.9) reduction instructions flag
+torture.generator.rvv.vmask       true  # RISC-V vector (v0.9) mask instructions flag
+torture.generator.rvv.vpermute    true  # RISC-V vector (v0.9) permutation instructions flag
+torture.generator.rvv.wide        true  # RISC-V vector (v0.9) widening (integer & floating-point) instructions flag
+torture.generator.rvv.narrow      true  # RISC-V vector (v0.9) narrowing (integer & floating-point) instructions flag
+torture.generator.rvv.masking     true  # for enabling masked instructions (by adding v0.t operand)
+
+torture.generator.rvv.multi_cfg   true  # for enabling multiple vector configurations in a single test (vfloat auto off)
+torture.generator.rvv.vlen        64    # parameter required for generating multiple vector configurations
+torture.generator.rvv.lmul        2     # RISC-V vector (v0.9) LMUL setting; valid: f2, f4, f8, 1, 2, 4, *8(wide/narrow => false)
+torture.generator.rvv.sew         32    # RISC-V vector (v0.9) SEW setting; valid: *8(vfloat => false), 16, 32, *64(wide/narrow => false for Spike), *(128, 256, 512, 1024) => (unsupported on Spike)
+torture.generator.rvv.nr          1     # RISC-V vector (v0.9) NR setting; valid: 1, 2, 4, 8
+torture.generator.rvv.nf          1     # RISC-V vector (v0.9) NF setting; valid: 1, *(2, 3, 4, 5, 6, 7, 8) => (for Zvlsseg)
+
+torture.testrun.maxcycles         1000000 # Maximum number of cycle for RTL and C simulation
+torture.testrun.virtual           false   # To run the test in virtual mode
+torture.testrun.seek              false   # Seek and report the failing program segment
+torture.testrun.dump              false   # To dump the data from RTL simulation in a file
+torture.testrun.vec               false   # Hwacha extension flag for Spike
+torture.testrun.rvv               true    # RISC-V vector (v0.9) extension flag for Spike
+
+torture.overnight.errors          1       # Set number of errors after which an error message will be emailed
+torture.overnight.minutes         1       # Set the time for running the test generator non-stop
+torture.overnight.outdir          output/failedtests  # To set the directory for failed tests
+torture.overnight.email           [email protected]  # Email for recieving error message
+
+NOTE:
+1. Spike (July 15th, 2020 commit) is programmed to have vector registers of length 64 bits.
+2. If testing gets stuck, try increasing the memory size or decreasing the nseqs parameter; or just restart.

config/default.config

@@ -1,52 +1,75 @@
-torture.generator.nseqs     200
-torture.generator.memsize   1024
-torture.generator.fprnd     0
-torture.generator.amo       true
-torture.generator.mul       true
-torture.generator.divider   true
-torture.generator.segment   true
-torture.generator.loop	    true
-torture.generator.loop_size 64
+torture.generator.nseqs           3000
+torture.generator.memsize         8192
+torture.generator.fprnd           0
+torture.generator.amo             true
+torture.generator.mul             true
+torture.generator.divider         true
+torture.generator.segment         true
+torture.generator.loop            true
+torture.generator.loop_size       64
 
-torture.generator.mix.xmem    10
-torture.generator.mix.xbranch 20
-torture.generator.mix.xalu    50
-torture.generator.mix.fgen    10
-torture.generator.mix.fpmem   5
-torture.generator.mix.fax     3
-torture.generator.mix.fdiv    2
-torture.generator.mix.vec     0
+torture.generator.mix.xmem        5
+torture.generator.mix.xbranch     5
+torture.generator.mix.xalu        10
+torture.generator.mix.fgen        20
+torture.generator.mix.fpmem       10
+torture.generator.mix.fax         10
+torture.generator.mix.fdiv        10
+torture.generator.mix.vec         0
+torture.generator.mix.rvv         30
 
-torture.generator.vec.vf 1
-torture.generator.vec.seq 20
-torture.generator.vec.memsize 128
-torture.generator.vec.numsregs 64
-torture.generator.vec.mul false
-torture.generator.vec.div false
-torture.generator.vec.mix true
-torture.generator.vec.fpu false
-torture.generator.vec.fma false
-torture.generator.vec.fcvt false
-torture.generator.vec.fdiv false
-torture.generator.vec.amo false
-torture.generator.vec.seg false
-torture.generator.vec.stride false
-torture.generator.vec.pred_alu true
-torture.generator.vec.pred_mem true
+torture.generator.vec.vf          1
+torture.generator.vec.seq         10
+torture.generator.vec.memsize     128
+torture.generator.vec.numsregs    64
+torture.generator.vec.mul         false
+torture.generator.vec.div         false
+torture.generator.vec.mix         true
+torture.generator.vec.fpu         false
+torture.generator.vec.fma         false
+torture.generator.vec.fcvt        false
+torture.generator.vec.fdiv        false
+torture.generator.vec.amo         false
+torture.generator.vec.seg         false
+torture.generator.vec.stride      false
+torture.generator.vec.pred_alu    true
+torture.generator.vec.pred_mem    true
 
-torture.generator.vec.mix.valu  20
-torture.generator.vec.mix.vpop  60
-torture.generator.vec.mix.vmem  20
-torture.generator.vec.mix.vonly 0
+torture.generator.vec.mix.valu    20
+torture.generator.vec.mix.vpop    60
+torture.generator.vec.mix.vmem    20
+torture.generator.vec.mix.vonly   0
 
-torture.testrun.maxcycles 10000000
-torture.testrun.virtual   false
-torture.testrun.seek      true
-torture.testrun.dump      false
-torture.testrun.vec       false
+torture.generator.rvv.vmem_unit   true
+torture.generator.rvv.vmem_const  true
+torture.generator.rvv.vmem_vect   true
+torture.generator.rvv.Zvlsseg     false
+torture.generator.rvv.Zvamo       false
+torture.generator.rvv.vfloat      true
+torture.generator.rvv.vinteger    true
+torture.generator.rvv.vfixed      true
+torture.generator.rvv.vreduce     true
+torture.generator.rvv.vmask       true
+torture.generator.rvv.vpermute    true
+torture.generator.rvv.wide        true
+torture.generator.rvv.narrow      true
+torture.generator.rvv.masking     true
 
-torture.overnight.errors  1
-torture.overnight.minutes 1
-torture.overnight.outdir  output/failedtests
-torture.overnight.email   [email protected]
+torture.generator.rvv.multi_cfg   true
+torture.generator.rvv.vlen        64
+torture.generator.rvv.lmul        2
+torture.generator.rvv.sew         32
+torture.generator.rvv.nr          1
+torture.generator.rvv.nf          1
 
+torture.testrun.maxcycles         1000000
+torture.testrun.virtual           false
+torture.testrun.seek              false
+torture.testrun.dump              false
+torture.testrun.vec               false
+torture.testrun.rvv               true
+
+torture.overnight.errors          1
+torture.overnight.minutes         1
+torture.overnight.outdir          output/failedtests
+torture.overnight.email           [email protected]