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Merge remote-tracking branch 'origin/dev' into chisel6
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jerryz123 committed Apr 20, 2024
2 parents a3eb23a + 58ad2f7 commit f924445
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Showing 5 changed files with 41 additions and 5 deletions.
2 changes: 1 addition & 1 deletion CHIPYARD.hash
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@@ -1 +1 @@
ef3409f87ff2988fa862ea48c995d2c27c93c7a2
b4aae0ddfdc5aaced32e0df90b633eab5b8327ca
2 changes: 1 addition & 1 deletion software/libgemmini
Submodule libgemmini updated 1 files
+1 −1 Makefile
2 changes: 1 addition & 1 deletion src/main/scala/gemmini/AccumulatorScale.scala
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Expand Up @@ -397,7 +397,7 @@ object AccumulatorScale {
val neg_q_iexp = neg(q)
val z_iexp = (neg_q_iexp * qln2_inv).asUInt.do_>>(16).asTypeOf(q) // q is non-positive
val z_iexp_saturated = Wire(z_iexp.cloneType)
z_iexp_saturated := Mux((5 until 16).map(z_iexp.asUInt(_)).reduce(_ | _), 32.S, z_iexp)
z_iexp_saturated := Mux((5 until 16).map(z_iexp.asUInt(_)).reduce(_ | _), 32.S.asTypeOf(z_iexp), z_iexp)
val qp_iexp = q.mac(z_iexp, qln2).withWidthOf(q)
val q_poly_iexp = qc.mac(qp_iexp + qb, qp_iexp + qb).withWidthOf(q)
// we dont want a rounding shift
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36 changes: 35 additions & 1 deletion src/main/scala/gemmini/ConfigsFP.scala
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Expand Up @@ -109,8 +109,30 @@ object GemminiFPConfigs {
mvin_scale_acc_args = Some(ScaleArguments((t: Float, u: Float) => t * u, 4, Float(8, 24), -1, identity = "1.0", c_str="((x) * (scale))")),
)

}

val chipFP32Config = FP32DefaultConfig.copy(sp_capacity=CapacityInKilobytes(32), acc_capacity=CapacityInKilobytes(8), dataflow=Dataflow.WS,
acc_scale_args = Some(ScaleArguments((t: Float, u: Float) => {t}, 1, Float(8, 24), -1, identity = "1.0",
c_str = "((x))"
)),
mvin_scale_args = Some(ScaleArguments((t: Float, u: Float) => t * u, 3, Float(8, 24), -1, identity = "1.0", c_str="((x) * (scale))")),
mvin_scale_acc_args=None,
acc_singleported=false,
acc_sub_banks = 1,
acc_banks = 2,
mesh_output_delay = 2,
tile_latency = 1,
acc_latency = 3,
ex_read_from_acc=false,
ex_write_to_spad=false,
has_training_convs = false,
hardcode_d_to_garbage_addr = true,
acc_read_full_width = false,
max_in_flight_mem_reqs = 16,
headerFileName = "gemmini_params_fp32.h",
num_counter = 0,
clock_gate = true
)
}

//===========FP32 Default Config=========
class GemminiFP32DefaultConfig extends Config((site, here, up) => {
Expand All @@ -123,6 +145,18 @@ class GemminiFP32DefaultConfig extends Config((site, here, up) => {
)
})

class ChipFP32GemminiConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiFPConfigs.chipFP32Config
) extends Config((site, here, up) => {
case BuildRoCC => up(BuildRoCC) ++ Seq(
(p: Parameters) => {
implicit val q = p
val gemmini = LazyModule(new Gemmini(gemminiConfig))
gemmini
}
)
})


//===========FP16 Default Config=========
class GemminiFP16DefaultConfig extends Config((site, here, up) => {
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4 changes: 3 additions & 1 deletion src/main/scala/gemmini/VectorScalarMultiplier.scala
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Expand Up @@ -198,6 +198,8 @@ object VectorScalarMultiplier {
) = {
assert(!is_acc || is_mvin)
val vsm = Module(new VectorScalarMultiplier(scale_args, cols, t, tag_t))
(vsm.io.req, vsm.io.resp)
val vsm_in_q = Module(new Queue(chiselTypeOf(vsm.io.req.bits), 2))
vsm.io.req <> vsm_in_q.io.deq
(vsm_in_q.io.enq, vsm.io.resp)
}
}

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