mmio gemmini rocc command

ucb-bar · Jan 19, 2024 · 8863f6f · 8863f6f
1 parent dffcfd1
commit 8863f6f
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Showing 2 changed files with 37 additions and 5 deletions.
diff --git a/software/gemmini-rocc-tests b/software/gemmini-rocc-tests
diff --git a/src/main/scala/gemmini/Controller.scala b/src/main/scala/gemmini/Controller.scala
@@ -9,9 +9,10 @@ import org.chipsalliance.cde.config._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tile._
 import freechips.rocketchip.util.ClockGate
-import freechips.rocketchip.tilelink.{TLBundle, TLClientNode, TLEdgeOut, TLFragmenter, TLIdentityNode, TLManagerNode, TLMasterParameters, TLMasterPortParameters, TLMasterToSlaveTransferSizes, TLRAM, TLSlaveParameters, TLSlavePortParameters, TLWidthWidget, TLXbar}
+import freechips.rocketchip.tilelink.{TLBundle, TLClientNode, TLEdgeOut, TLFragmenter, TLIdentityNode, TLManagerNode, TLMasterParameters, TLMasterPortParameters, TLMasterToSlaveTransferSizes, TLRAM, TLRegisterNode, TLSlaveParameters, TLSlavePortParameters, TLWidthWidget, TLXbar}
 import GemminiISA._
 import Util._
+import freechips.rocketchip.regmapper.RegField
 
 class GemminiCmd(rob_entries: Int)(implicit p: Parameters) extends Bundle {
  val cmd = new RoCCCommand
@@ -142,6 +143,16 @@ class Gemmini[T <: Data : Arithmetic, U <: Data, V <: Data](val config: GemminiA
 
  val node = if (config.use_dedicated_tl_port) tlNode else atlNode
 
+ val regDevice = new SimpleDevice("gemmini-cmd-reg", Seq(s"gemmini-cmd-reg"))
+ val regNode = TLRegisterNode(
+ address = Seq(AddressSet(0x60000000, 0xfff)),
+ device = regDevice,
+ beatBytes = 8,
+ concurrency = 1)
+
+ regNode := TLFragmenter(8, 64) := stlNode
+
+
  unified_mem_write_node := spad.spad_writer.node
 }
 
@@ -345,14 +356,35 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
  clock_en_reg := io.cmd.bits.rs1(0)
  }
 
+ val regValid = Wire(Bool())
+ val regCommand = Wire(io.cmd.bits.cloneType)
+ val gemminiRs1Reg = RegInit(0.U.asTypeOf(io.cmd.bits.rs1.cloneType))
+ val gemminiRs2Reg = RegInit(0.U.asTypeOf(io.cmd.bits.rs2.cloneType))
+ regCommand.rs1 := gemminiRs1Reg
+ regCommand.rs2 := gemminiRs2Reg
+ regCommand.status := io.cmd.bits.status
+
  val raw_cmd_q = Module(new Queue(new GemminiCmd(reservation_station_entries), entries = 2))
- raw_cmd_q.io.enq.valid := io.cmd.valid
- io.cmd.ready := raw_cmd_q.io.enq.ready
- raw_cmd_q.io.enq.bits.cmd := io.cmd.bits
+ raw_cmd_q.io.enq.valid := regValid || io.cmd.valid
+ io.cmd.ready := raw_cmd_q.io.enq.ready && !regValid
+ raw_cmd_q.io.enq.bits.cmd := Mux(regValid, regCommand, io.cmd.bits)
  raw_cmd_q.io.enq.bits.rob_id := DontCare
  raw_cmd_q.io.enq.bits.from_conv_fsm := false.B
  raw_cmd_q.io.enq.bits.from_matmul_fsm := false.B
 
+ def gemminiCommandReg(valid: Bool, bits: UInt): Bool = {
+ regValid := valid
+ regCommand.inst := bits.asTypeOf(regCommand.inst)
+ // when(valid && raw_cmd_q.io.enq.ready)
+ raw_cmd_q.io.enq.ready
+ }
+
+ outer.regNode.regmap(
+ 0x00 -> Seq(RegField.w(32, gemminiCommandReg(_, _))),
+ 0x10 -> Seq(RegField.w(64, gemminiRs1Reg)),
+ 0x18 -> Seq(RegField.w(64, gemminiRs2Reg))
+ )
+
  val raw_cmd = raw_cmd_q.io.deq
 
  val max_lds = reservation_station_entries_ld