transfer size fix

ucb-bar · Apr 1, 2024 · 5de43ae · 5de43ae
1 parent a92e231
commit 5de43ae
Showing 1 changed file with 7 additions and 2 deletions.
diff --git a/src/main/scala/gemmini/Controller.scala b/src/main/scala/gemmini/Controller.scala
@@ -64,15 +64,20 @@ class Gemmini[T <: Data : Arithmetic, U <: Data, V <: Data](val config: GemminiA
  TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
  name = s"spad_read_node_$i",
  sourceId = IdRange(0, num_ids),
- visibility = Seq(AddressSet(spad_base + i * mem_width * mem_depth, mem_width * mem_depth - 1))
+ visibility = Seq(AddressSet(spad_base + i * mem_width * mem_depth, mem_width * mem_depth - 1)),
+ supportsProbe = TransferSizes(mem_width, mem_width),
+ supportsGet = TransferSizes(mem_width, mem_width)
  )))
  }) else TLIdentityNode()
 
  val spad_write_nodes = if (use_ext_tl_mem) TLClientNode(Seq.tabulate(config.sp_banks) { i =>
  TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
  name = s"spad_write_node_$i",
  sourceId = IdRange(0, num_ids),
- visibility = Seq(AddressSet(spad_base + i * mem_width * mem_depth, mem_width * mem_depth - 1))
+ visibility = Seq(AddressSet(spad_base + i * mem_width * mem_depth, mem_width * mem_depth - 1)),
+ supportsProbe = TransferSizes(mem_width, mem_width),
+ supportsPutFull = TransferSizes(mem_width, mem_width),
+ supportsPutPartial = TransferSizes(mem_width, mem_width)
  )))
  }) else TLIdentityNode()