Bump toolchains/riscv-tools/riscv-isa-sim from 3c5b1bb to cb78f09
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Bumps [toolchains/riscv-tools/riscv-isa-sim](https://github.com/riscv-software-src/riscv-isa-sim) from `3c5b1bb` to `cb78f09`. - [Release notes](https://github.com/riscv-software-src/riscv-isa-sim/releases) - [Commits](riscv-software-src/riscv-isa-sim@3c5b1bb...cb78f09) --- updated-dependencies: - dependency-name: toolchains/riscv-tools/riscv-isa-sim dependency-type: direct:production ... Signed-off-by: dependabot[bot] <[email protected]>
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Bumps toolchains/riscv-tools/riscv-isa-sim from
3c5b1bbtocb78f09.Commits
cb78f09Merge pull request #1797 from YenHaoChen/pr-vector6a1a5dbvector: disassemble: Let operand ordering be vd, [vf]s1, vs2 to vector wideni...b47d0bavector: disassemble: Let operand ordering be vd, [vf]s1, vs2 to vector single...7f38a50vector: disassemble: Let operand ordering be vd, [vr]s1, vs2 to vector wideni...ff62109vector: disassemble: Let operand ordering be vd, [vr]s1, vs2 to vector single...2538c1fMerge pull request #1788 from riscv-software-src/support-larger-addresses52f045dLift restriction on physical-address size1687094Use create_mem_region for legacy -m argumenteb85c33Check size_t bounds overflow in create_mem_region1b33b54Factor out create_mem_region from parse_mem_layoutDependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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