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Add example accelerator using HLS
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.. _incorporating-hls: | ||
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Incorporating HLS | ||
============================ | ||
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High Level Synthesis (HLS) is a method for iterating quickly on | ||
different hardware algorithms that automatically generates an RTL | ||
circuit to match a specification in a high level language like C. | ||
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Here, we will integrate an HLS-generated accelerator that computes | ||
the Great Common Denominator (GCD) of two integers. This tutorial | ||
builds on the sections :ref:`mmio-accelerators` and | ||
:ref:`incorporating-verilog-blocks`. | ||
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Adding an HLS project | ||
--------------------------------------- | ||
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In this tutorial, we use Vitis HLS. The user guide for this tool | ||
can be found at https://docs.amd.com/r/en-US/ug1399-vitis-hls. | ||
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Our project consists of 3 HLS files: | ||
* C program of the GCD algorithm: :gh-file-ref:`generators/chipyard/src/main/resources/hls/HLSAccel.cpp` | ||
* TCL script to run Vitis HLS: :gh-file-ref:`generators/chipyard/src/main/resources/hls/run_hls.tcl` | ||
* Makefile to run HLS and move verilog files: :gh-file-ref:`generators/chipyard/src/main/resources/hls/Makefile` | ||
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This example implements an iterative GCD algorithm, which is manually connected to | ||
a TileLink register node in the ``HLSGCDAccel`` class in | ||
:gh-file-ref:`generators/chipyard/src/main/scala/example/GCD.scala`. | ||
HLS also supports adding AXI nodes to accelerators using compiler directives and | ||
the HLS stream library. See the Vitis HLS user guide for AXI implementation information. | ||
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The HLS code is synthesized for a particular FPGA target, in this case, | ||
an AMD Alveo U200. The target FPGA part is specified in ``run_hls.tcl`` using | ||
the ``set_part command``. The clock period, used for design optimization purposes, | ||
is also set in ``run_hls.tcl`` using the ``create_clock`` command. | ||
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To generate the verilog files, as well as synthesis reports, run: | ||
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.. code-block:: none | ||
vitis_hls run_hls.tcl | ||
The files can be found in a generated folder named proj\_\<your\_project\_name>, | ||
in our case, ``proj_gcd_example``. | ||
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In our case, we include a ``Makefile`` to run HLS and to move files to | ||
their intended locations. To generate the verilog files using the Makefile, run: | ||
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.. code-block:: none | ||
make | ||
To delete the generated files, run: | ||
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.. code-block:: none | ||
make clean | ||
Creating the Verilog black box | ||
--------------------------------------- | ||
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.. Note:: This section discusses automatically running HLS within a Verilog black box. Please consult :ref:`incorporating-verilog-blocks` for background information on writing a Verilog black box. | ||
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We use Scala to run ``make``, which runs HLS and copies the files into :gh-file-ref:`generators/chipyard/src/main/resources/vsrc`. | ||
Then, we add the path to each file. This code will execute during Chisel elaboration, conveniently handling | ||
file generation for the user. | ||
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.. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala | ||
:language: scala | ||
:start-after: DOC include start: HLS blackbox | ||
:end-before: DOC include end: HLS blackbox | ||
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Running the example | ||
--------------------------------------- | ||
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To test if the accelerator works, use the test program in :gh-file-ref:`tests/gcd.c`. | ||
Compile the program with ``make``. Then, run: | ||
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.. code-block:: none | ||
cd sims/vcs | ||
make run-binary CONFIG=HLSAcceleratorRocketConfig BINARY=../../tests/gcd.riscv |
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#ifndef _GCD_EX_H_ | ||
#define _GCD_EX_H_ | ||
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#include <ap_int.h> | ||
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#define DATA_WIDTH 32 | ||
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typedef ap_uint<DATA_WIDTH> io_t; | ||
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io_t HLSGCDAccelBlackBox(io_t x, io_t y) { | ||
io_t tmp; | ||
io_t gcd; | ||
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tmp = y; | ||
gcd = x; | ||
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while(tmp != 0) { | ||
if (gcd > tmp) { | ||
gcd = gcd - tmp; | ||
} else { | ||
tmp = tmp - gcd; | ||
} | ||
} | ||
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return gcd; | ||
} | ||
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#endif |
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base_dir=$(abspath ../../../..) | ||
hls_dir=$(abspath .) | ||
hls_vlog_gendir=$(hls_dir)/proj_gcd_example/solution1/syn/verilog | ||
vsrc_dir=$(base_dir)/src/main/resources/vsrc | ||
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.PHONY: default run-hls clean | ||
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HLS_CMD = vitis_hls | ||
TCL_SCRIPT = run_hls.tcl | ||
ACCEL_C = HLSAccel.cpp | ||
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default: run-hls | ||
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run-hls: $(ACCEL_C) $(TCL_SCRIPT) | ||
$(HLS_CMD) $(TCL_SCRIPT) | ||
cp -r $(hls_vlog_gendir)/. $(vsrc_dir) | ||
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clean: | ||
rm -rf $(hls_dir)/proj_gcd_example | ||
rm -f $(hls_dir)/vitis_hls.log | ||
rm -f $(vsrc_dir)/HLSGCDAccelBlackBox* |
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open_project -reset proj_gcd_example | ||
add_files HLSAccel.cpp | ||
set_top HLSGCDAccelBlackBox | ||
open_solution -reset "solution1" | ||
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# Specify FPGA board and clock frequency | ||
set_part {xcu200-fsgd2104-2-e} | ||
create_clock -period 10 | ||
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csynth_design | ||
exit |
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