💻 Simple-As-Possible (SAP-1) 8-bit Computer Using Proteus

This project is an implementation of the SAP-1 (Simple As Possible) 8-bit computer architecture using Proteus. It showcases the fundamental workings of a computer, including a processing unit, control unit, and memory unit, built using discrete components. This project serves as a foundational step for understanding more intricate computer architectures.

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📜 Project Overview

SAP stands for "Simple As Possible." Originally introduced by Albert Paul Malvino and Jerald A. Brown, the SAP architecture lays the groundwork for modern computer fundamentals.
The architecture includes:

1. Processing Unit: Performs arithmetic and logical operations.
2. Control Unit: Manages the execution of instructions.
3. Memory Unit: Stores data and instructions.

Three types of SAP architectures exist: SAP-1, SAP-2, and SAP-3. This project focuses on SAP-1, designed as a basic yet powerful computer model.

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🏗️ Architecture of SAP-1

Key Features:

1. 8-bit Bus

   • Facilitates data transfer within the system.
   • Video: Explanation of 8-bit Bus

2. 16x8-bit RAM

   • Stores instructions and data.
   • Video: 16x8-bit RAM Design

3. 4-bit Program Counter (PC)

   • Keeps track of the instruction address.
   • Video: Program Counter Design

4. Input Unit and Memory Address Register (MAR)

   • MAR selects memory locations for instruction fetching.
   • Video: MAR Design

5. 8-bit Arithmetic Logic Unit (ALU)

   • Performs arithmetic and logical operations.
   • Video: ALU Design

6. Accumulator (Register A) and Register B

   • Temporarily stores data for computations.
   • Video: Accumulator and Register B Design

7. Clock

   • Synchronizes operations within the system.
   • Video: Clock Design

8. 3-Bit BCD Display

   • Converts binary output to BCD for readability.
   • Video: BCD Display Design

9. Control Sequencer

   • Generates control signals for executing instructions.
   • Video: Control Sequencer Design

10. Instruction Register

    • Holds the current instruction for decoding and execution.
    • Video: Instruction Register Design

11. Address Selector

    • Determines the next instruction address.
    • Video: Address Selector Design

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🔍 Project Testing

The system's functionality was tested using Proteus simulations.

• Video: Project Testing

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✨ Special Features

1. T-State Reduction:
   • Reduced the T-states from 6 to 4 for improved performance.
2. Binary to BCD Display:
   • Added an 8-bit binary to 3-bit BCD converter for better readability.
3. Negative Number Handling:
   • Displays a minus (-) sign for subtraction when the result is negative.

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🛠️ How to Use

1. Clone the Repository:

   git clone https://github.com/touhidulislam1999/Simple-As-Possible-SAP-8-bit-computer-using-Proteus.git