rggen / rggen Star 324 Code Issues Pull requests Discussions Code generation tool for control and status registers asic fpga vhdl eda rtl verilog csr systemverilog soc uvm ral axi amba apb register-descriptions wishbone-bus uvm-ral-model uvm-register-model wiki-documents Updated Jul 20, 2024 Ruby
SystemRDL / PeakRDL-uvm Star 50 Code Issues Pull requests Generate UVM register model from compiled SystemRDL input asic fpga eda uvm registers uvm-ral-model uvm-register-model Updated Sep 3, 2024 Python
rggen / rggen-sample-testbench Star 14 Code Issues Pull requests vhdl verilog systemverilog uvm uvm-ral-model uvm-register-model Updated Jun 3, 2024 VHDL
kumarrishav14 / arm_watchdog Star 9 Code Issues Pull requests Verification IP for Watchdog arm uvm watchdog-timer uvm-ral-model arm-watchdog Updated Apr 6, 2021 SystemVerilog
rggen / rggen-sv-ral Star 6 Code Issues Pull requests UVM RAL class package for RgGen systemverilog uvm ral uvm-ral-model uvm-register-model Updated Feb 1, 2024 SystemVerilog
ganesh-rgb / VLSI-Design-Projects- Star 0 Code Issues Pull requests Electronics Circuit Design and Verification verilog systemverilog uvm uvm-ral-model digitalelectronics analog-circuit-design testbench-development Updated Oct 3, 2024 Verilog