IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
-
Updated
Dec 23, 2024 - Python
#
microelectronics
Here are 41 public repositories matching this topic...
Rsyn – An Extensible Physical Synthesis Framework
-
Updated
Jul 20, 2024 - C++
Development repository for ViennaPS, a fully-fledged semiconductor fabrication process simulation library.
-
Updated
Dec 19, 2024 - C++
A repository for embedded systems learning portals
arduino gpio i2c electronics gnu-linux adafruit gcc embedded-systems spi pi4j rs232 avr-programming pwm embedded-linux microelectronics dynamic-memory-allocation c-programming-language engineering-books embedded-engineering dynamic-memory-management
-
Updated
Oct 29, 2022 - Markdown
Simple UVM phase jumping
-
Updated
Feb 6, 2020 - SystemVerilog
A tool for matching devices in analog layout
-
Updated
Feb 11, 2023 - Python
A personal collection of documents usually describing cutting-edge technology and research
-
Updated
Jul 10, 2017
Simulating ADC background calibration algorithms in OpenCL
python simulation electronics opencl calibration adc heterogeneous-parallel-programming ica microelectronics analog-to-digital-converter
-
Updated
Oct 25, 2023 - Python
Repository for open-source tools to VLSI design
-
Updated
Jul 18, 2024 - Shell
Julia port of Prof. Boris Murmann's gm/ID Starter Kit https://web.stanford.edu/~murmann/gmid
-
Updated
Dec 29, 2022 - Julia
3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.
design communication-protocol pipeline digital hardware electronics signal-processing processor master-slave verilog fft vivado intellectual-property c-programming integrated-circuits microblaze axi interconnect microelectronics vitis
-
Updated
Apr 13, 2024 - VHDL
A Personal blog describing various technical and research works.
-
Updated
Jun 21, 2018 - CSS
FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.
design fpga communication-protocol digital hardware electronics processor master-slave verilog vivado floating-point intellectual-property c-programming integrated-circuits microblaze axi interconnect microelectronics vitis arty-s7
-
Updated
Apr 13, 2024 - VHDL
DLX processor implementation and improvement
-
Updated
Jul 18, 2017 - Verilog
Implementation of 2-bit & 8-bit CMOS microelectronic circuit simulations in HSpice
electronics spice circuit circuit-simulation comparator cmos microelectronics hspice electronic-simulation cmos-circuits
-
Updated
Aug 6, 2024 - SourcePawn
Python-based electronic design automation (EDA) tool for characterizing digital standard cells designed in SKY130 PDK. The characterization process is based in the Synopsys Liberty User Guides and Reference Manual Suite - Version 2017.06
-
Updated
Jan 10, 2024 - Python
Exercício 02 de SystemVerilog
-
Updated
Dec 8, 2016 - SystemVerilog
Python I2C driver for 3rd party ST LPS22 pressure sensor
-
Updated
May 13, 2024 - Python
A universal device that allows improving modern traffic lights and adapting them for people with disabilities.
-
Updated
Mar 26, 2022 - C++
Improve this page
Add a description, image, and links to the microelectronics topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the microelectronics topic, visit your repo's landing page and select "manage topics."