Update userGuide.md

docs/userGuide.md

@@ -63,7 +63,7 @@ Click the `Simulation` tab which is located on the top-right corner and then `St
 
 and check that the output is correct based on the truth table of the AND gate.
 
-![](../img/userGuide/firstDesignSim.gif)
+![](img/userGuide/firstDesignSim.gif)
 
 
 **Well Done!** You just completed your first ISSIE design. 
@@ -82,7 +82,7 @@ This section will exploit the features of ISSIE to create clean and good-looking
 - Add a new 1-bit output `RESULT` 
 - Make all necessary connections by dragging as before to achieve a diagram like the one bellow:
 
-![](../img/userGuide/features1.png)
+![](img/userGuide/features1.png)
 
 Again, **simulate the design** and check the output remains correct as you change the values of the 4 inputs
 
@@ -100,7 +100,7 @@ You can view the shortcuts for all these modifications by clicking on the `edit`
 
 **The improved schematic:**
 
-![](../img/userGuide/features2.gif)
+![](img/userGuide/features2.gif)
 
 
 ### Summary
@@ -132,7 +132,7 @@ Steps:
 4. Using 3 `SplitWire` components (`BUSES` => `SplitWire`) separate the 4-bit ROM output to 4 1-bit wires. (see image below)
 5. Make the appropriate connections to achieve the schematic below
 
-![](../img/userGuide/custom.png)
+![](img/userGuide/custom.png)
 
 ### Improving the design sheet
 
@@ -141,7 +141,7 @@ It's time to use a hidden part of the Issie UI to **move ports on custom symbols
 
 Preview how it works in the gif below:
 
-![](../img/userGuide/custom2.gif)
+![](img/userGuide/custom2.gif)
 
 
 ### ROM Initialisation
@@ -172,7 +172,7 @@ Add a `Counter` from the Catalogue (`FLIP FLOPS AND REGISTERS`). Now select the
 
 Create a schematic like the one below:
 
-![](../img/userGuide/waveform.png)
+![](img/userGuide/waveform.png)
 
 ### Simulating your design
 
@@ -192,7 +192,7 @@ As soon as you connect everything correctly, You can simulate your design. Click
 - Check that the waveform simulator output matches your previous (Step Simulation) results.
 - Drag the grey horizontal divider to make the waveforms larger or smaller (you can do this at any time).
 
-![](../img/userGuide/waveform1.png)
+![](img/userGuide/waveform1.png)
 
 
 ### Changing your design
@@ -201,7 +201,7 @@ As soon as you connect everything correctly, You can simulate your design. Click
 Now, keeping the simulation open, add an extra register between the counter and the ROM address (or make any other change you want) and check that the simulation has the expected output. You can see the changes in the waveform simulator by clicking the `Refresh` button which will be enabled as soon as it detects a change in the schematic. 
 
 
-![](../img/userGuide/waveform2.png)
+![](img/userGuide/waveform2.png)
 
 ## Truth Table
 
@@ -213,7 +213,7 @@ One of ISSIE's features is the ability to view the truth table for a small combi
 - Click on `Remove Redundancies`
 - The truth table should look like this:
 
-![](../img/userGuide/truthTable1.png)
+![](img/userGuide/truthTable1.png)
 
 
 You can also select your inputs to be **algebraic values** to get an expression for each of your outputs.
@@ -223,13 +223,13 @@ You can also select your inputs to be **algebraic values** to get an expression
 - Select the inputs you want to be algebraic values
 - Truth table should now look like this:
 
-![](../img/userGuide/truthTable2.png)
+![](img/userGuide/truthTable2.png)
 
 ## Verilog Component
 
 Last but not least, ISSIE allows you to create combinational custom components by defining the logic in Verilog. Click on `Verilog` -> `New Verilog Component` (Catalogue) and write the logic of your decoder in Verilog.
 
-![](../img/userGuide/verilog1.png)
+![](img/userGuide/verilog1.png)
 
 - Click `Save`
 - Replace the previous Decoder with the new one (found under `Verilog` section in the Catalogue)