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Fixes for counter trigger #53

Merged
merged 9 commits into from
Mar 14, 2023
2 changes: 1 addition & 1 deletion Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -63,7 +63,7 @@ all: linux
daq_bitfiles: $(addsuffix .bit, $(addprefix bitfiles/daq_,$(DAQ_PARTS)))

bitfiles/daq_%.bit: daq_cores
ifneq ("$(wildcard bitfiles/daq_$*.bit)","")
ifeq ("$(wildcard bitfiles/daq_$*.bit)","")
vivado -nolog -nojournal -mode batch -source src/fpga/build.tcl -tclargs $*
vivado -nolog -nojournal -mode batch -source scripts/runSynthAndImpl.tcl -tclargs $*
mkdir -p bitfiles
Expand Down
2 changes: 1 addition & 1 deletion scripts/alpine.sh
Original file line number Diff line number Diff line change
Expand Up @@ -102,7 +102,7 @@ cp -r ../../linux-image/alpine/etc $root_dir/
mkdir -p $root_dir/media/mmcblk0p1/apps

# Copy current status of RedPitayaDAQServer directory
rsync -av -q ../../ $root_dir/media/mmcblk0p1/apps/RedPitayaDAQServer --exclude build --exclude .Xil --exclude "red-pitaya-alpine*.zip"
rsync -av -q ../../ $root_dir/media/mmcblk0p1/apps/RedPitayaDAQServer --exclude build --exclude tmp --exclude .Xil --exclude "red-pitaya-alpine*.zip" --exclude *.jou --exclude *.log --exclude vivado*.str

# Reset repository
git remote set-url origin https://github.com/tknopp/RedPitayaDAQServer.git
Expand Down
4 changes: 2 additions & 2 deletions src/fpga/bd/bd.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -3396,11 +3396,11 @@ proc create_root_design { parentCell } {
assign_bd_address -offset 0x80028000 -range 0x00008000 -target_address_space [get_bd_addr_spaces system/processing_system7_0/Data] [get_bd_addr_segs fourier_synth_standard/signal_compose1/waveform_awg1/axi_bram_ctrl_0/S_AXI/Mem0] -force
assign_bd_address -offset 0x80020000 -range 0x00008000 -target_address_space [get_bd_addr_spaces system/processing_system7_0/Data] [get_bd_addr_segs fourier_synth_standard/signal_compose/waveform_awg/axi_bram_ctrl_0/S_AXI/Mem0] -force
assign_bd_address -offset 0x40004000 -range 0x00001000 -target_address_space [get_bd_addr_spaces system/processing_system7_0/Data] [get_bd_addr_segs system/axi_cfg_register_cfg/s_axi/reg0] -force
assign_bd_address -offset 0x40002800 -range 0x00000800 -target_address_space [get_bd_addr_spaces system/processing_system7_0/Data] [get_bd_addr_segs system/axi_cfg_register_counter_trigger/s_axi/reg0] -force
assign_bd_address -offset 0x40008000 -range 0x00001000 -target_address_space [get_bd_addr_spaces system/processing_system7_0/Data] [get_bd_addr_segs system/axi_cfg_register_counter_trigger/s_axi/reg0] -force
assign_bd_address -offset 0x40000000 -range 0x00001000 -target_address_space [get_bd_addr_spaces system/processing_system7_0/Data] [get_bd_addr_segs system/axi_cfg_register_dac/s_axi/reg0] -force
assign_bd_address -offset 0x40006000 -range 0x00001000 -target_address_space [get_bd_addr_spaces system/processing_system7_0/Data] [get_bd_addr_segs system/axi_sts_register_DIOIn/s_axi/reg0] -force
assign_bd_address -offset 0x40001000 -range 0x00001000 -target_address_space [get_bd_addr_spaces system/processing_system7_0/Data] [get_bd_addr_segs system/axi_sts_register_adc/s_axi/reg0] -force
assign_bd_address -offset 0x40002000 -range 0x00000800 -target_address_space [get_bd_addr_spaces system/processing_system7_0/Data] [get_bd_addr_segs system/axi_sts_register_counter_trigger/s_axi/reg0] -force
assign_bd_address -offset 0x40007000 -range 0x00001000 -target_address_space [get_bd_addr_spaces system/processing_system7_0/Data] [get_bd_addr_segs system/axi_sts_register_counter_trigger/s_axi/reg0] -force
assign_bd_address -offset 0x40003000 -range 0x00001000 -target_address_space [get_bd_addr_spaces system/processing_system7_0/Data] [get_bd_addr_segs system/axi_sts_register_pdm/s_axi/reg0] -force
assign_bd_address -offset 0x40005000 -range 0x00001000 -target_address_space [get_bd_addr_spaces system/processing_system7_0/Data] [get_bd_addr_segs system/axi_sts_register_reset/s_axi/reg0] -force
assign_bd_address -offset 0x40010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces system/processing_system7_0/Data] [get_bd_addr_segs xadc_wiz_0/s_axi_lite/Reg] -force
Expand Down
61 changes: 30 additions & 31 deletions src/lib/rp-daq-lib.c
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,8 @@ bool verbose = false;
int mmapfd;
volatile uint32_t *slcr, *axi_hp0;
void *pdm_sts, *reset_sts, *cfg, *ram, *dio_sts;
uint32_t *counter_trigger;
uint32_t *counter_trigger_cfg;
uint32_t *counter_trigger_sts;
uint16_t *pdm_cfg;
uint64_t *adc_sts, *dac_cfg;
uint32_t *awg_0_cfg, *awg_1_cfg;
Expand All @@ -38,8 +39,6 @@ static const uint32_t ANALOG_IN_MAX_VAL_INTEGER = 0xFFF;
// static const float ANALOG_OUT_MIN_VAL = 0.0;
// static const uint32_t ANALOG_OUT_MAX_VAL_INTEGER = 156;

static const uint32_t COUNTER_TRIGGER_CFG_OFFSET = 0x800/sizeof(int32_t);

// Cached parameter values.
static rp_calib_params_t calib;

Expand Down Expand Up @@ -144,14 +143,14 @@ int init() {
pdm_sts = mmap(NULL, sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, mmapfd, 0x40003000);
reset_sts = mmap(NULL, sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, mmapfd, 0x40005000);
dio_sts = mmap(NULL, sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, mmapfd, 0x40006000);
counter_trigger = mmap(NULL, sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, mmapfd, 0x40002000);
counter_trigger_cfg = mmap(NULL, sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, mmapfd, 0x40008000);
counter_trigger_sts = mmap(NULL, sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, mmapfd, 0x40007000);
cfg = mmap(NULL, sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, mmapfd, 0x40004000);
ram = mmap(NULL, sizeof(int32_t)*ADC_BUFF_SIZE, PROT_READ|PROT_WRITE, MAP_SHARED, mmapfd, ADC_BUFF_MEM_ADDRESS);
xadc = mmap(NULL, 16*sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, mmapfd, 0x40010000);
awg_0_cfg = mmap(NULL, AWG_BUFF_SIZE*sizeof(uint32_t)/2, PROT_READ|PROT_WRITE, MAP_SHARED, mmapfd, 0x80020000);
awg_1_cfg = mmap(NULL, AWG_BUFF_SIZE*sizeof(uint32_t)/2, PROT_READ|PROT_WRITE, MAP_SHARED, mmapfd, 0x80028000);



loadBitstream();

calib_Init(); // Load calibration from EEPROM
Expand Down Expand Up @@ -1505,12 +1504,12 @@ uint32_t cmn_CalibFullScaleFromVoltage(float voltageScale) {
}

/**
* Memory layout for `counter_trigger + COUNTER_TRIGGER_CFG_OFFSET` upper bits 0x40002800
* Memory layout for `counter_trigger_cfg` upper bits 0x40008000
*
* 0 ................................................................................................................. 67 bit |
* reference_counter (32 bit) | presamples (32 bit) | enable (1 bit) | arm (1 bit) | reset (1 bit) | source selection (5 bit) |
*
* Memory layout for `counter_trigger` lower bits 0x40002000
* Memory layout for `counter_trigger_sts` lower bits 0x40007000
*
* 0 ............................ 33 bit |
* last_counter (32 bit) | armed (1 bit) |
Expand All @@ -1521,49 +1520,49 @@ int counter_trigger_setEnabled(bool enable) {
counter_trigger_disarm(); // Always disarm when disabling
}

uint32_t register_value = *(counter_trigger + COUNTER_TRIGGER_CFG_OFFSET + 2);
uint32_t register_value = *(counter_trigger_cfg + 2);
if (enable) {
register_value = register_value | (1 << 0);
}
else {
register_value = register_value & ~(1 << 0);
}

*(counter_trigger + COUNTER_TRIGGER_CFG_OFFSET + 2) = register_value;
*(counter_trigger_cfg + 2) = register_value;
return 0;
}

bool counter_trigger_isEnabled() {
uint32_t register_value = *(counter_trigger + COUNTER_TRIGGER_CFG_OFFSET + 2);
uint32_t register_value = *(counter_trigger_cfg + 2);
register_value = register_value & (1 << 0);
return (register_value > 0);
}

int counter_trigger_setPresamples(uint32_t presamples) {
*(counter_trigger + COUNTER_TRIGGER_CFG_OFFSET + 1) = presamples;
*(counter_trigger_cfg + 1) = presamples;
return 0;
}

int counter_trigger_getPresamples() {
return *(counter_trigger + COUNTER_TRIGGER_CFG_OFFSET + 1);
return *(counter_trigger_cfg + 1);
}

int counter_trigger_arm() {
uint32_t register_value = *(counter_trigger + COUNTER_TRIGGER_CFG_OFFSET + 2);
uint32_t register_value = *(counter_trigger_cfg + 2);
register_value = register_value | (1 << 1);
*(counter_trigger + COUNTER_TRIGGER_CFG_OFFSET + 2) = register_value;
*(counter_trigger_cfg + 2) = register_value;
return 0;
}

int counter_trigger_disarm() {
uint32_t register_value = *(counter_trigger + COUNTER_TRIGGER_CFG_OFFSET + 2);
uint32_t register_value = *(counter_trigger_cfg + 2);
register_value = register_value & ~(1 << 1);
*(counter_trigger + COUNTER_TRIGGER_CFG_OFFSET + 2) = register_value;
*(counter_trigger_cfg + 2) = register_value;
return 0;
}

bool counter_trigger_isArmed() {
uint32_t register_value = *(counter_trigger + 1);
uint32_t register_value = *(counter_trigger_sts + 1);
register_value = register_value & (1 << 0);
return (register_value > 0);
}
Expand All @@ -1573,51 +1572,51 @@ int counter_trigger_setReset(bool reset) {
counter_trigger_disarm(); // Always disarm when resetting
}

uint32_t register_value = *(counter_trigger + COUNTER_TRIGGER_CFG_OFFSET + 2);
uint32_t register_value = *(counter_trigger_cfg + 2);
if (reset) {
register_value = register_value | (1 << 2);
}
else {
register_value = register_value & ~(1 << 2);
}

*(counter_trigger + COUNTER_TRIGGER_CFG_OFFSET + 2) = register_value;
*(counter_trigger_cfg + 2) = register_value;
return 0;
}

bool counter_trigger_getReset() {
uint32_t register_value = *(counter_trigger + COUNTER_TRIGGER_CFG_OFFSET + 2);
uint32_t register_value = *(counter_trigger_cfg + 2);
register_value = register_value & (1 << 2);
return (register_value > 0);
}

uint32_t counter_trigger_getLastCounter() {
return *(counter_trigger + 0);
return *(counter_trigger_sts + 0);
}

int counter_trigger_setReferenceCounter(uint32_t reference_counter) {
*(counter_trigger + COUNTER_TRIGGER_CFG_OFFSET + 0) = reference_counter;
*(counter_trigger_cfg + 0) = reference_counter;
return 0;
}

uint32_t counter_trigger_getReferenceCounter() {
return *(counter_trigger + COUNTER_TRIGGER_CFG_OFFSET + 0);
return *(counter_trigger_cfg + 0);
}

uint32_t counter_trigger_getSelectedChannelType() {
uint32_t register_value = *(counter_trigger + COUNTER_TRIGGER_CFG_OFFSET + 2);
uint32_t register_value = *(counter_trigger_cfg + 2);
return (register_value & (1 << 7)) >> 7;
}

bool counter_trigger_setSelectedChannelType(uint32_t channelType) {
uint32_t register_value = *(counter_trigger + COUNTER_TRIGGER_CFG_OFFSET + 2);
uint32_t register_value = *(counter_trigger_cfg + 2);
if (channelType == COUNTER_TRIGGER_ADC)
{
*(counter_trigger + COUNTER_TRIGGER_CFG_OFFSET + 2) = register_value | (1 << 7);
*(counter_trigger_cfg + 2) = register_value | (1 << 7);
}
else if (channelType == COUNTER_TRIGGER_DIO)
{
*(counter_trigger + COUNTER_TRIGGER_CFG_OFFSET + 2) = register_value & ~(1 << 7);
*(counter_trigger_cfg + 2) = register_value & ~(1 << 7);
}
else
{
Expand All @@ -1628,7 +1627,7 @@ bool counter_trigger_setSelectedChannelType(uint32_t channelType) {
}

char* counter_trigger_getSelectedChannel() {
uint32_t register_value = *(counter_trigger + COUNTER_TRIGGER_CFG_OFFSET + 2);
uint32_t register_value = *(counter_trigger_cfg + 2);
uint32_t channelNumber = (register_value & (0b1111 << 3)) >> 3;
if (counter_trigger_getSelectedChannelType() == COUNTER_TRIGGER_DIO) {
return getPinFromInternalPINNumber(channelNumber);
Expand Down Expand Up @@ -1661,7 +1660,7 @@ uint32_t counter_trigger_setSelectedChannel(const char* channel) {
return channelNumber;
}

uint32_t register_value = *(counter_trigger + COUNTER_TRIGGER_CFG_OFFSET + 2);
*(counter_trigger + COUNTER_TRIGGER_CFG_OFFSET + 2) = (register_value | (0b1111 << 3)) & ((channelNumber << 3) | ~(0b1111 << 3));
uint32_t register_value = *(counter_trigger_cfg + 2);
*(counter_trigger_cfg + 2) = (register_value | (0b1111 << 3)) & ((channelNumber << 3) | ~(0b1111 << 3));
return 0;
}
2 changes: 1 addition & 1 deletion src/lib/rp-daq-lib.h
Original file line number Diff line number Diff line change
Expand Up @@ -64,7 +64,7 @@ extern int mmapfd;
extern volatile uint32_t *slcr, *axi_hp0;
// FPGA registers that are memory mapped
extern void *pdm_sts, *reset_sts, *cfg, *ram, *buf, *dio_sts;
extern void *counter_trigger_cfg, *counter_trigger_sts;
extern uint32_t *counter_trigger_cfg, *counter_trigger_sts;
extern uint16_t *pdm_cfg;
extern uint64_t *adc_sts, *dac_cfg;
extern uint32_t *awg_0_cfg, *awg_1_cfg;
Expand Down
11 changes: 5 additions & 6 deletions src/server/daq_server_scpi.c
Original file line number Diff line number Diff line change
Expand Up @@ -230,6 +230,11 @@ int main(int argc, char** argv) {

logger_flush();

if(!initialized) {
init();
initialized = true;
}

int rc;
int listenfd;

Expand All @@ -250,7 +255,6 @@ int main(int argc, char** argv) {
// Ignore SIGPIPE signal to ensure that process is not silently terminated
sigaction(SIGPIPE, &(struct sigaction){SIG_IGN}, NULL);


getprio(pthread_self());

/* User_context will be pointer to socket */
Expand Down Expand Up @@ -288,11 +292,6 @@ int main(int argc, char** argv) {
if(controlThreadRunning) {
joinControlThread();
}

if(!initialized) {
init();
initialized = true;
}

newdatasocklen = sizeof(newdatasockaddr);
newdatasockfd = accept(datasockfd, (struct sockaddr *) &newdatasockaddr, &newdatasocklen);
Expand Down