Fix counter trigger (#59)

* Slight simplification to counter trigger code

* Fix timing problems

* Move export

src/client/julia/src/Cluster.jl

@@ -1,8 +1,10 @@
-export RedPitayaCluster, master, numChan, ClusterTriggerSetup, ALL_INTERNAL, ALL_EXTERNAL, MASTER_EXTERNAL
+export RedPitayaCluster, master, numChan
 
 import Base: length, iterate, getindex, firstindex, lastindex
 
+export ClusterTriggerSetup, ALL_INTERNAL, ALL_EXTERNAL, MASTER_EXTERNAL
 @enum ClusterTriggerSetup ALL_INTERNAL ALL_EXTERNAL MASTER_EXTERNAL
+
 """
     RedPitayaCluster
 

src/fpga/hdl/counter_delayed_trigger.v

@@ -7,7 +7,7 @@ module counter_delayed_trigger #
 	parameter integer ADC_WIDTH = 16
 )
 (
-    input clk,
+  input clk,
 	input enable,
 	input trigger_arm, // Arm the trigger
 	input trigger_reset, // Unset the trigger after having triggered. Needs re-arming then.
@@ -19,7 +19,7 @@ module counter_delayed_trigger #
 	input [TRIGGER_COUNTER_WIDTH-1:0] reference_counter, // The reference that is used for determining when to start the trigger. Note: Splitted off to allow for e.g using an average value of the polled last counter values.
 	output trigger, // The actual trigger
 	output trigger_armed, // Arming status of the trigger
-    output [TRIGGER_COUNTER_WIDTH-1:0] last_counter // The last full counter value
+  output [TRIGGER_COUNTER_WIDTH-1:0] last_counter // The last full counter value
 );
 
 // Delayed trigger counter
@@ -146,7 +146,7 @@ begin
 				end
 
 				// Only do internal arming when we would not directly trigger due to already satisfying the condition
-				if ((trigger_armed_int_pre == 1) && ~(delayed_trigger_counter >= reference_counter-trigger_presamples-1))
+				if ((trigger_armed_int_pre == 1) && ~(delayed_trigger_counter >= reference_counter-trigger_presamples-1) && (last_counter_out > 1))
 				begin
 					trigger_armed_int <= 1;
 				end
@@ -165,14 +165,7 @@ begin
 		trigger_armed_int_pre <= 0;
 
 		// If the counter trigger is not enabled, it should always be on due to and-ing the triggers
-		if (enable == 1)
-		begin
-			trigger_out <= 0;
-		end
-		else
-		begin
-			trigger_out <= 1;
-		end
+		trigger_out <= 1;
 	end
 end
 

src/fpga/hdl/reset_manager.v

@@ -5,7 +5,6 @@ module reset_manager #
     parameter integer ALIVE_SIGNAL_LOW_TIME = 100, // in milliseconds
     parameter integer ALIVE_SIGNAL_HIGH_TIME = 10, // in milliseconds
     parameter integer RAMWRITER_DELAY = 1 // in milliseconds
-
 )
 (
     input clk,