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Add basic support for FIT image on the AARCH64 architecture, reuse exsitting DSC and FDF files for IA32, X64 and AARCH64 architectures. Introduce new PCD: PcdUseUniversalPayloadSerialPort to indicate which serial port module is used due to some serial port parameters are fixed for ARM SoC and Platform. Please use following command to build AARCH64 UPL FIT image: " export GCC5_AARCH64_PREFIX=aarch64-linux-gnu- python UefiPayloadPkg/UniversalPayloadBuild.py -a AARCH64 -t GCC5 -b DEBUG --Fit " Signed-off-by: Amos Bu <[email protected]> Signed-off-by: Ajan Zhong <[email protected]>
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/** @file | ||
Generic version of arch-specific functionality for DxeLoad. | ||
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR> | ||
Copyright 2024 Google LLC | ||
SPDX-License-Identifier: BSD-2-Clause-Patent | ||
**/ | ||
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#include <PiPei.h> | ||
#include <Library/BaseLib.h> | ||
#include <Library/DebugLib.h> | ||
#include <Library/BaseMemoryLib.h> | ||
#include <Library/MemoryAllocationLib.h> | ||
#include <Library/PcdLib.h> | ||
#include <Library/HobLib.h> | ||
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#include "UefiPayloadEntry.h" | ||
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#define STACK_SIZE 0x20000 | ||
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/** | ||
Transfers control to DxeCore. | ||
This function performs a CPU architecture specific operations to execute | ||
the entry point of DxeCore with the parameters of HobList. | ||
It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase. | ||
@param DxeCoreEntryPoint The entry point of DxeCore. | ||
@param HobList The start of HobList passed to DxeCore. | ||
**/ | ||
VOID | ||
HandOffToDxeCore ( | ||
IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint, | ||
IN EFI_PEI_HOB_POINTERS HobList | ||
) | ||
{ | ||
VOID *BaseOfStack; | ||
VOID *TopOfStack; | ||
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// | ||
// Allocate 128KB for the Stack | ||
// | ||
BaseOfStack = AllocatePages (EFI_SIZE_TO_PAGES (STACK_SIZE)); | ||
ASSERT (BaseOfStack != NULL); | ||
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// | ||
// Compute the top of the stack we were allocated. Pre-allocate a UINTN | ||
// for safety. | ||
// | ||
TopOfStack = (VOID *)((UINTN)BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT); | ||
TopOfStack = ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT); | ||
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// | ||
// Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore. | ||
// | ||
UpdateStackHob ((EFI_PHYSICAL_ADDRESS)(UINTN)BaseOfStack, STACK_SIZE); | ||
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// | ||
// Transfer the control to the entry point of DxeCore. | ||
// | ||
SwitchStack ( | ||
(SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint, | ||
HobList.Raw, | ||
NULL, | ||
TopOfStack | ||
); | ||
} |
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/** @file | ||
aarch64-specifc functionality for Module Entry Point. | ||
Copyright 2024 Google LLC | ||
SPDX-License-Identifier: BSD-2-Clause-Patent | ||
**/ | ||
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#include "UefiPayloadEntry.h" | ||
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/** | ||
Entry point to the C language phase of UEFI payload. | ||
@param[in] FdtBaseAddr Pointer to the FDT | ||
@param[in] AdditionalPara Not used yet | ||
@retval It will not return if SUCCESS, and return error | ||
when passing bootloader parameter. | ||
**/ | ||
EFI_STATUS | ||
EFIAPI | ||
_ModuleEntryPoint ( | ||
IN UINTN FdtBaseAddr, | ||
IN UINTN AddtionalPara | ||
) | ||
{ | ||
return FitUplEntryPoint (FdtBaseAddr); | ||
} |
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