OvmfPkg: RiscVVirt: Add missing SerialPortInitialize to Sec

If the SerialPortLib had any initialization needed, this would be skipped in the RiscVVirt Sec. Follow the example seen elsewhere (ArmVirtPkg PrePi). Seen with BaseSerialPortLibRiscVSbiLibRam not using DBCN in Sec, yet using DBCN elsewhere. Cc: Daniel Schaefer <[email protected]> Signed-off-by: Andrei Warkentin <[email protected]> Reviewed-by: Sunil V L <[email protected]> Reviewed-by: Michael D Kinney <[email protected]>
tianocore · May 17, 2023 · 0abfb0b · 0abfb0b
1 parent 45da4e3
commit 0abfb0b
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Showing 3 changed files with 5 additions and 1 deletion.
diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.c b/OvmfPkg/RiscVVirt/Sec/SecMain.c
@@ -1,7 +1,7 @@
 /** @file
   RISC-V SEC phase module for Qemu Virt.
 
-  Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
   Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -57,6 +57,8 @@ SecStartup (
   UINT64                      StackBase;
   UINT32                      StackSize;
 
+  SerialPortInitialize ();
+
   //
   // Report Status Code to indicate entering SEC core
   //

diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.h b/OvmfPkg/RiscVVirt/Sec/SecMain.h
@@ -29,6 +29,7 @@
 #include <Library/PrePiLib.h>
 #include <Library/PlatformInitLib.h>
 #include <Library/PrePiHobListPointerLib.h>
+#include <Library/SerialPortLib.h>
 #include <Register/RiscV64/RiscVImpl.h>
 
 /**

diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.inf b/OvmfPkg/RiscVVirt/Sec/SecMain.inf
@@ -48,6 +48,7 @@
   FdtLib
   MemoryAllocationLib
   HobLib
+  SerialPortLib
 
 [Ppis]
   gEfiTemporaryRamSupportPpiGuid                # PPI ALWAYS_PRODUCED
-Original file line number
+Diff line change
@@ Expand Up / @@ -48,6 +48,7 @@ @@
       FdtLib
       MemoryAllocationLib
       HobLib
+      SerialPortLib
     [Ppis]
       gEfiTemporaryRamSupportPpiGuid                # PPI ALWAYS_PRODUCED
@@ Expand Down @@