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Upstream pcie v2 #199

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Upstream pcie v2 #199

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7dcf45f
Silicon/Bosc: Added PciSegmentLib to NanHuDev
Sep 4, 2024
8f8ae61
Silicon/Bosc:Added PciHostBridgeLib to NanHuDev
Sep 12, 2024
f26fe1f
Silicon/Bosc:Added NVME driver to NanHuDev
Sep 12, 2024
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30 changes: 29 additions & 1 deletion Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.dsc
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Original file line number Diff line number Diff line change
Expand Up @@ -239,6 +239,9 @@
PlatformBootManagerLib|Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
PlatformMemoryTestLib|Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf
PlatformUpdateProgressLib|Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf
# Pci dependencies
PciSegmentLib|Silicon/Bosc/NanHuPkg/Library/PciSegmentLib/PciSegmentLib.inf
PciHostBridgeLib|Silicon/Bosc/NanHuPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf

[LibraryClasses.common.UEFI_APPLICATION]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
Expand All @@ -262,6 +265,24 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE

[PcdsFixedAtBuild]
#
# XILINX PCI Root Complex
#
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x40000000
gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE
gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation|0x0
gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation|0x50000000
gBoscNanHuDdevPlatformPkgTokenSpaceGuid.PcdPciConfigBase|0x40000000
gBoscNanHuDdevPlatformPkgTokenSpaceGuid.PcdPciConfigSize|0x10000000
gBoscNanHuDdevPlatformPkgTokenSpaceGuid.PcdPciBusMin|0
gBoscNanHuDdevPlatformPkgTokenSpaceGuid.PcdPciBusMax|255
gBoscNanHuDdevPlatformPkgTokenSpaceGuid.PcdPciIoBase|0x00000
gBoscNanHuDdevPlatformPkgTokenSpaceGuid.PcdPciIoSize|0xf00000
gBoscNanHuDdevPlatformPkgTokenSpaceGuid.PcdPciMmio32Base|0x50000000
gBoscNanHuDdevPlatformPkgTokenSpaceGuid.PcdPciMmio32Size|0x10000000
gBoscNanHuDdevPlatformPkgTokenSpaceGuid.PcdPciMmio64Base|0x1000000000
gBoscNanHuDdevPlatformPkgTokenSpaceGuid.PcdPciMmio64Size|0x0000000000

gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1
Expand Down Expand Up @@ -427,11 +448,13 @@
MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
!endif

UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf {
<LibraryClasses>
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
}
MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
MdeModulePkg/Universal/Metronome/Metronome.inf
MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf {
Expand All @@ -440,6 +463,11 @@
}
EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf

#
# NVME Support
#
MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf

#
# RISC-V Platform module
#
Expand Down
13 changes: 11 additions & 2 deletions Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.fdf
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Expand Up @@ -69,8 +69,6 @@ INF OvmfPkg/Fdt/HighMemDxe/HighMemDxe.inf

INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
INF MdeModulePkg/Universal/Metronome/Metronome.inf
INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf

Expand Down Expand Up @@ -127,6 +125,17 @@ INF ShellPkg/Application/Shell/Shell.inf

!include NetworkPkg/Network.fdf.inc

#
# PCI Support
#
INF Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf

# NVMe boot devices
#
INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf

#
# Usb Support
#
Expand Down
177 changes: 177 additions & 0 deletions Silicon/Bosc/NanHuPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
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@@ -0,0 +1,177 @@
/** @file
PCI host bridge library instance for NanHuDev SOC.

Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
Copyright (c) 2024, Bosc. All rights reserved.<BR>ved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent

**/

#include <Library/DebugLib.h>
#include <Library/DevicePathLib.h>
#include <Library/PciHostBridgeLib.h>
#include <Library/IoLib.h>

#include "PciHostBridgeLib.h"

#pragma pack(1)

typedef struct {
ACPI_HID_DEVICE_PATH AcpiDevicePath;
EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;

#pragma pack ()

STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
{
ACPI_DEVICE_PATH_DEF (0),
END_DEVICE_PATH_DEF
},
};

GLOBAL_REMOVE_IF_UNREFERENCED
CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
L"Mem", L"I/O", L"Bus"
};

STATIC PCI_ROOT_BRIDGE mRootBridge = {
0, // Segment
0, // Supports
0, // Attributes
FALSE, // DmaAbove4G
FALSE, // NoExtendedConfigSpace
FALSE, // ResourceAssigned
0, // AllocationAttributes
{
// Bus
FixedPcdGet32 (PcdPciBusMin),
FixedPcdGet32 (PcdPciBusMax)
}, {
// Io
FixedPcdGet64 (PcdPciIoBase),
FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1
}, {
// Mem
FixedPcdGet32 (PcdPciMmio32Base),
FixedPcdGet32 (PcdPciMmio32Base) + (FixedPcdGet32 (PcdPciMmio32Size) - 1)
//0x7FFFFFFF
}, {
// MemAbove4G
FixedPcdGet64 (PcdPciMmio64Base),
FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - 1
}, {
// PMem
MAX_UINT64,
0
}, {
// PMemAbove4G
MAX_UINT64,
0
},
(EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath
};

/**
Return all the root bridge instances in an array.

@param[out] Count Return the count of root bridge instances.

@return All the root bridge instances in an array.
The array should be passed into PciHostBridgeFreeRootBridges()
when it's not used.

**/
PCI_ROOT_BRIDGE *
EFIAPI
PciHostBridgeGetRootBridges (
OUT UINTN *Count
)
{
/* Enable the Bridge enable bit */
UINT64 PciConfigBase = FixedPcdGet64 (PcdPciConfigBase);
UINT32 Rpsc = MmioRead32 (PciConfigBase + XILINX_PCIE_REG_RPSC);
MmioWrite32 (PciConfigBase + XILINX_PCIE_REG_RPSC, Rpsc | XILINX_PCIE_REG_RPSC_BEN);
DEBUG ((DEBUG_INFO, "PciHostBridgeGetRootBridges():%d PciConfigBase:0x%x Rpsc:0x%x XILINX_PCIE_REG_RPSC_BEN:0x%x\n", \
__LINE__, PciConfigBase, Rpsc, Rpsc | XILINX_PCIE_REG_RPSC_BEN));

*Count = 1;
return &mRootBridge;
}


/**
Free the root bridge instances array returned from PciHostBridgeGetRootBridges().

@param[in] Bridges The root bridge instances array.
@param[in] Count The count of the array.

**/
VOID
EFIAPI
PciHostBridgeFreeRootBridges (
IN PCI_ROOT_BRIDGE *Bridges,
IN UINTN Count
)
{

}


/**
Inform the platform that the resource conflict happens.

@param[in] HostBridgeHandle Handle of the Host Bridge.
@param[in] Configuration Pointer to PCI I/O and PCI memory resource
descriptors. The Configuration contains the resources
for all the root bridges. The resource for each root
bridge is terminated with END descriptor and an
additional END is appended indicating the end of the
entire resources. The resource descriptor field
values follow the description in
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
SubmitResources().

**/
VOID
EFIAPI
PciHostBridgeResourceConflict (
IN EFI_HANDLE HostBridgeHandle,
IN VOID *Configuration
)
{
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
BOOLEAN IsPrefetchable;

Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
ASSERT (Descriptor->ResType <
ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr));
DEBUG ((DEBUG_INFO, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
Descriptor->AddrLen,
Descriptor->AddrRangeMax
));
if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {

IsPrefetchable = (Descriptor->SpecificFlag &
EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) != 0;

DEBUG ((DEBUG_INFO, " Granularity/SpecificFlag = %ld / %02x%s\n",
Descriptor->AddrSpaceGranularity,
Descriptor->SpecificFlag,
(IsPrefetchable) ? L" (Prefetchable)" : L""
));
}
}
//
// Skip the end descriptor for root bridge
//
ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) (
(EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
);
}
}
33 changes: 33 additions & 0 deletions Silicon/Bosc/NanHuPkg/Library/PciHostBridgeLib/PciHostBridgeLib.h
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/** @file
Main Header file for the PciHostBridgeLib

Copyright (c) 2024, Bosc. All rights reserved.<BR>ved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent

**/
#ifndef __PCIHOSTBRIDGELIB_H
#define __PCIHOSTBRIDGELIB_H

#define BIT(nr) (1UL << (nr))
#define GENMASK(h, l) \
(((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h))))

/* Register definitions */
#define XILINX_PCIE_REG_RPSC (0x00000148)

/* Root Port Status/control Register definitions */
#define XILINX_PCIE_REG_RPSC_BEN BIT(0)

#define END_DEVICE_PATH_DEF { END_DEVICE_PATH_TYPE, \
END_ENTIRE_DEVICE_PATH_SUBTYPE, \
{ END_DEVICE_PATH_LENGTH, 0 } \
}

#define ACPI_DEVICE_PATH_DEF(UID) {{ ACPI_DEVICE_PATH, ACPI_DP, \
{ (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \
(UINT8) (sizeof (ACPI_HID_DEVICE_PATH) >> 8)} \
}, \
EISA_PNP_ID (0x0A03), UID \
}
#endif
49 changes: 49 additions & 0 deletions Silicon/Bosc/NanHuPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
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#/** @file
# PCI Host Bridge Library instance for Bosc SOC.
#
# Copyright (C) 2020, Bosc Technology Co, Ltd. All rights reserved.<BR>
# Copyright (c) 2024, Bosc. All rights reserved.<BR>ved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/

[Defines]
INF_VERSION = 0x0001001b
BASE_NAME = PciHostBridgeLib
FILE_GUID = 7F418E45-0127-454E-9CBB-F5FCF237E383
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER

#
# The following information is for reference only and not required by the build
# tools.
#
# VALID_ARCHITECTURES = RISCV64
#

[Sources]
PciHostBridgeLib.h
PciHostBridgeLib.c

[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Silicon/Bosc/NanHuPkg/NanHuDevPkg.dec

[LibraryClasses]
DebugLib

[Guids]

[FixedPcd]
gBoscNanHuDdevPlatformPkgTokenSpaceGuid.PcdPciBusMin
gBoscNanHuDdevPlatformPkgTokenSpaceGuid.PcdPciBusMax
gBoscNanHuDdevPlatformPkgTokenSpaceGuid.PcdPciIoBase
gBoscNanHuDdevPlatformPkgTokenSpaceGuid.PcdPciIoSize
gBoscNanHuDdevPlatformPkgTokenSpaceGuid.PcdPciMmio32Base
gBoscNanHuDdevPlatformPkgTokenSpaceGuid.PcdPciMmio32Size
gBoscNanHuDdevPlatformPkgTokenSpaceGuid.PcdPciMmio64Base
gBoscNanHuDdevPlatformPkgTokenSpaceGuid.PcdPciMmio64Size
gBoscNanHuDdevPlatformPkgTokenSpaceGuid.PcdPciConfigBase
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