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Silicon/Bosc:Added PciHostBridgeLib to NanHuDev
Reviewed-by: Evan Chai <[email protected]> Reviewed-by: Ran Wang <[email protected]> Reviewed-by: Jian Zhang <[email protected]> Cc: Sunil V L <[email protected]> Cc: Leif Lindholm <[email protected]> Cc: Michael D Kinney <[email protected]> Cc: Daniel Schaefer <[email protected]> Cc: Ray Ni <[email protected]> Signed-off-by: Yang Wang <[email protected]>
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178 changes: 178 additions & 0 deletions
178
Silicon/Bosc/NanHuPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
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| Original file line number | Diff line number | Diff line change |
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| /** @file | ||
| PCI host bridge library instance for NanHuDev SOC. | ||
| Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> | ||
| Copyright (c) 2024, Bosc. All rights reserved.<BR> | ||
| SPDX-License-Identifier: BSD-2-Clause-Patent | ||
| **/ | ||
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| #include <Library/DebugLib.h> | ||
| #include <Library/DevicePathLib.h> | ||
| #include <Library/PciHostBridgeLib.h> | ||
| #include <Library/IoLib.h> | ||
| #include <RiscVBitOp.h> | ||
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| #include "PciHostBridgeLib.h" | ||
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| #pragma pack(1) | ||
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| typedef struct { | ||
| PCI_DEVICE_PATH PciDevicePath; | ||
| EFI_DEVICE_PATH_PROTOCOL EndDevicePath; | ||
| } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; | ||
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| #pragma pack () | ||
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| STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = { | ||
| { | ||
| PCI_DEVICE_PATH_NODE(0, 0), | ||
| END_DEVICE_PATH_DEF | ||
| }, | ||
| }; | ||
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| GLOBAL_REMOVE_IF_UNREFERENCED | ||
| CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = { | ||
| L"Mem", L"I/O", L"Bus" | ||
| }; | ||
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| STATIC PCI_ROOT_BRIDGE mRootBridge = { | ||
| 0, // Segment | ||
| 0, // Supports | ||
| 0, // Attributes | ||
| FALSE, // DmaAbove4G | ||
| FALSE, // NoExtendedConfigSpace | ||
| FALSE, // ResourceAssigned | ||
| 0, // AllocationAttributes | ||
| { | ||
| // Bus | ||
| FixedPcdGet32 (PcdPciBusMin), | ||
| FixedPcdGet32 (PcdPciBusMax) | ||
| }, { | ||
| // Io | ||
| FixedPcdGet64 (PcdPciIoBase), | ||
| FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1 | ||
| }, { | ||
| // Mem | ||
| FixedPcdGet32 (PcdPciMmio32Base), | ||
| FixedPcdGet32 (PcdPciMmio32Base) + (FixedPcdGet32 (PcdPciMmio32Size) - 1) | ||
| //0x7FFFFFFF | ||
| }, { | ||
| // MemAbove4G | ||
| FixedPcdGet64 (PcdPciMmio64Base), | ||
| FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - 1 | ||
| }, { | ||
| // PMem | ||
| MAX_UINT64, | ||
| 0 | ||
| }, { | ||
| // PMemAbove4G | ||
| MAX_UINT64, | ||
| 0 | ||
| }, | ||
| (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath | ||
| }; | ||
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| /** | ||
| Return all the root bridge instances in an array. | ||
| @param[out] Count Return the count of root bridge instances. | ||
| @return All the root bridge instances in an array. | ||
| The array should be passed into PciHostBridgeFreeRootBridges() | ||
| when it's not used. | ||
| **/ | ||
| PCI_ROOT_BRIDGE * | ||
| EFIAPI | ||
| PciHostBridgeGetRootBridges ( | ||
| OUT UINTN *Count | ||
| ) | ||
| { | ||
| /* Enable the Bridge enable bit */ | ||
| UINT64 PciConfigBase = FixedPcdGet64 (PcdPciConfigBase); | ||
| UINT32 Rpsc = MmioRead32 (PciConfigBase + XILINX_PCIE_REG_RPSC); | ||
| MmioWrite32 (PciConfigBase + XILINX_PCIE_REG_RPSC, Rpsc | XILINX_PCIE_REG_RPSC_BEN); | ||
| DEBUG ((DEBUG_INFO, "%a: PciConfigBase:0x%x Rpsc:0x%x\n", __func__, PciConfigBase)); | ||
| DEBUG ((DEBUG_INFO, "%a: Rpsc:0x%x \n", __func__, Rpsc)); | ||
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| *Count = 1; | ||
| return &mRootBridge; | ||
| } | ||
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| /** | ||
| Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). | ||
| @param[in] Bridges The root bridge instances array. | ||
| @param[in] Count The count of the array. | ||
| **/ | ||
| VOID | ||
| EFIAPI | ||
| PciHostBridgeFreeRootBridges ( | ||
| IN PCI_ROOT_BRIDGE *Bridges, | ||
| IN UINTN Count | ||
| ) | ||
| { | ||
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| } | ||
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| /** | ||
| Inform the platform that the resource conflict happens. | ||
| @param[in] HostBridgeHandle Handle of the Host Bridge. | ||
| @param[in] Configuration Pointer to PCI I/O and PCI memory resource | ||
| descriptors. The Configuration contains the resources | ||
| for all the root bridges. The resource for each root | ||
| bridge is terminated with END descriptor and an | ||
| additional END is appended indicating the end of the | ||
| entire resources. The resource descriptor field | ||
| values follow the description in | ||
| EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL | ||
| SubmitResources(). | ||
| **/ | ||
| VOID | ||
| EFIAPI | ||
| PciHostBridgeResourceConflict ( | ||
| IN EFI_HANDLE HostBridgeHandle, | ||
| IN VOID *Configuration | ||
| ) | ||
| { | ||
| EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; | ||
| BOOLEAN IsPrefetchable; | ||
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| Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; | ||
| while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) { | ||
| for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) { | ||
| ASSERT (Descriptor->ResType < | ||
| ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr)); | ||
| DEBUG ((DEBUG_INFO, " %s: Length/Alignment = 0x%lx / 0x%lx\n", | ||
| mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType], | ||
| Descriptor->AddrLen, | ||
| Descriptor->AddrRangeMax | ||
| )); | ||
| if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) { | ||
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| IsPrefetchable = (Descriptor->SpecificFlag & | ||
| EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) != 0; | ||
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| DEBUG ((DEBUG_INFO, " Granularity/SpecificFlag = %ld / %02x%s\n", | ||
| Descriptor->AddrSpaceGranularity, | ||
| Descriptor->SpecificFlag, | ||
| (IsPrefetchable) ? L" (Prefetchable)" : L"" | ||
| )); | ||
| } | ||
| } | ||
| // | ||
| // Skip the end descriptor for root bridge | ||
| // | ||
| ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR); | ||
| Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) ( | ||
| (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 | ||
| ); | ||
| } | ||
| } |
37 changes: 37 additions & 0 deletions
37
Silicon/Bosc/NanHuPkg/Library/PciHostBridgeLib/PciHostBridgeLib.h
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| @@ -0,0 +1,37 @@ | ||
| /** @file | ||
| Main Header file for the PciHostBridgeLib | ||
| Copyright (c) 2024, Bosc. All rights reserved.<BR>ved.<BR> | ||
| SPDX-License-Identifier: BSD-2-Clause-Patent | ||
| **/ | ||
| #ifndef __PCIHOSTBRIDGELIB_H | ||
| #define __PCIHOSTBRIDGELIB_H | ||
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| /* Register definitions */ | ||
| #define XILINX_PCIE_REG_RPSC (0x00000148) | ||
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| /* Root Port Status/control Register definitions */ | ||
| #define XILINX_PCIE_REG_RPSC_BEN BIT(0) | ||
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| #define END_DEVICE_PATH_DEF { END_DEVICE_PATH_TYPE, \ | ||
| END_ENTIRE_DEVICE_PATH_SUBTYPE, \ | ||
| { END_DEVICE_PATH_LENGTH, 0 } \ | ||
| } | ||
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| #define PCI_DEVICE_PATH_NODE(Func, Dev) \ | ||
| { \ | ||
| { \ | ||
| HARDWARE_DEVICE_PATH, \ | ||
| HW_PCI_DP, \ | ||
| { \ | ||
| (UINT8) (sizeof (PCI_DEVICE_PATH)), \ | ||
| (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) \ | ||
| } \ | ||
| }, \ | ||
| (Func), \ | ||
| (Dev) \ | ||
| } | ||
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| #endif |
49 changes: 49 additions & 0 deletions
49
Silicon/Bosc/NanHuPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,49 @@ | ||
| #/** @file | ||
| # PCI Host Bridge Library instance for Bosc SOC. | ||
| # | ||
| # Copyright (c) 2024, Bosc. All rights reserved.<BR> | ||
| # | ||
| # SPDX-License-Identifier: BSD-2-Clause-Patent | ||
| # | ||
| #**/ | ||
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| [Defines] | ||
| INF_VERSION = 0x0001001b | ||
| BASE_NAME = PciHostBridgeLib | ||
| FILE_GUID = 7F418E45-0127-454E-9CBB-F5FCF237E383 | ||
| MODULE_TYPE = DXE_DRIVER | ||
| VERSION_STRING = 1.0 | ||
| LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER | ||
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| # | ||
| # The following information is for reference only and not required by the build | ||
| # tools. | ||
| # | ||
| # VALID_ARCHITECTURES = RISCV64 | ||
| # | ||
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| [Sources] | ||
| PciHostBridgeLib.h | ||
| PciHostBridgeLib.c | ||
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| [Packages] | ||
| MdePkg/MdePkg.dec | ||
| MdeModulePkg/MdeModulePkg.dec | ||
| Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec | ||
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| [LibraryClasses] | ||
| DebugLib | ||
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| [Guids] | ||
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| [FixedPcd] | ||
| gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciConfigBase | ||
| gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciConfigSize | ||
| gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciBusMin | ||
| gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciBusMax | ||
| gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciIoBase | ||
| gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciIoSize | ||
| gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio32Base | ||
| gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio32Size | ||
| gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio64Base | ||
| gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio64Size |
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