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Merge pull request #358 from tactcomplabs/conversions
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Enable -Wconversion warnings to avoid inadvertent lowering conversions
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@leekillough
leekillough authored Jan 10, 2025
2 parents df83e82 + e20036f commit a6efaaf
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Showing 27 changed files with 207 additions and 209 deletions.
4 changes: 2 additions & 2 deletions CMakeLists.txt
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@@ -1,5 +1,5 @@
# RevCPU Top-Level CMake
# Copyright (C) 2017-2024 Tactical Computing Laboratories, LLC
# Copyright (C) 2017-2025 Tactical Computing Laboratories, LLC
# All Rights Reserved
# [email protected]
# See LICENSE in the top level directory for licensing details
Expand Down Expand Up @@ -83,7 +83,7 @@ else()
set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wmissing-format-attribute -Wsuggest-final-methods -Wsuggest-final-types -Wvolatile")
endif()

set(CMAKE_CXX_FLAGS "-std=c++17 ${FP_MODE_FLAG} -O2 -Wall -Wextra -Wsuggest-override -Wmissing-noreturn -Wvla -Wuninitialized -Wdouble-promotion -Wsign-conversion -Wno-unused-parameter -Wno-deprecated-declarations -Wno-macro-redefined -Werror ${CMAKE_CXX_FLAGS} -I./ ${LDFLAGS} ${REVCPU_COMPILER_MACROS}")
set(CMAKE_CXX_FLAGS "-std=c++17 ${FP_MODE_FLAG} -O2 -Wall -Wextra -Wsuggest-override -Wmissing-noreturn -Wvla -Wuninitialized -Wdouble-promotion -Wsign-conversion -Wconversion -Wno-unused-parameter -Wno-deprecated-declarations -Wno-macro-redefined -Werror ${CMAKE_CXX_FLAGS} -I./ ${LDFLAGS} ${REVCPU_COMPILER_MACROS}")
set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} -O0 -Wall ${REVCPU_COMPILER_MACROS}")
set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} -O3 -Wall ${REVCPU_COMPILER_MACROS}")

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4 changes: 2 additions & 2 deletions common/include/RevCommon.h
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@@ -1,7 +1,7 @@
//
// _Rev_Common_h_
//
// Copyright (C) 2017-2024 Tactical Computing Laboratories, LLC
// Copyright (C) 2017-2025 Tactical Computing Laboratories, LLC
// All Rights Reserved
// [email protected]
//
Expand Down Expand Up @@ -62,7 +62,7 @@ constexpr T&& make_dependent( T&& x ) {
template<typename T>
constexpr auto ZeroExt( T val, int bits ) {
using UT = std::make_unsigned_t<T>;
return UT( val & ~( UT( ~UT{} ) << bits ) );
return UT( UT( val ) & UT( ~( UT( ~UT{} ) << bits ) ) );
}

/// Sign-extend value of bits size
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4 changes: 2 additions & 2 deletions include/RevCPU.h
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@@ -1,7 +1,7 @@
//
// _RevCPU_h_
//
// Copyright (C) 2017-2024 Tactical Computing Laboratories, LLC
// Copyright (C) 2017-2025 Tactical Computing Laboratories, LLC
// All Rights Reserved
// [email protected]
//
Expand Down Expand Up @@ -266,7 +266,7 @@ class RevCPU : public SST::Component {
uint8_t PrivTag{}; ///< RevCPU: private tag locator
// uint32_t LToken{}; ///< RevCPU: token identifier for PAN Test

int address{ -1 }; ///< RevCPU: local network address
int64_t address{ -1 }; ///< RevCPU: local network address

uint32_t fault_width{}; ///< RevCPU: the width (in bits) for target faults
// int64_t fault_range{}; ///< RevCPU: the range of cycles to inject the fault
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38 changes: 22 additions & 16 deletions include/RevCSR.h
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@@ -1,7 +1,7 @@
//
// _RevCSR_h_
//
// Copyright (C) 2017-2024 Tactical Computing Laboratories, LLC
// Copyright (C) 2017-2025 Tactical Computing Laboratories, LLC
// All Rights Reserved
// [email protected]
//
Expand Down Expand Up @@ -464,29 +464,29 @@ struct RevCSR : RevZicntr {
};

///< RevCSR: Register a custom getter for a particular CSR register
void SetCSRGetter( uint16_t csr, std::function<uint64_t( uint16_t )> handler ) {
void SetCSRGetter( uint32_t csr, std::function<uint64_t( uint32_t )> handler ) {
handler ? (void) Getter.insert_or_assign( csr, std::move( handler ) ) : (void) Getter.erase( csr );
}

///< RevCSR: Register a custom setter for a particular CSR register
void SetCSRSetter( uint16_t csr, std::function<bool( uint16_t, uint64_t )> handler ) {
void SetCSRSetter( uint32_t csr, std::function<bool( uint32_t, uint64_t )> handler ) {
handler ? (void) Setter.insert_or_assign( csr, std::move( handler ) ) : (void) Setter.erase( csr );
}

///< RevCSR: Get the custom getter for a particular CSR register
// If no custom getter exists for this RevCSR, look for one in the owning RevCore
template<typename CSR>
auto GetCSRGetter( CSR csr ) const {
template<typename T = void>
auto GetCSRGetter( uint32_t csr ) const {
auto it = Getter.find( csr );
return it != Getter.end() && it->second ? it->second : make_dependent<CSR>( GetCore() )->GetCSRGetter( csr );
return it != Getter.end() && it->second ? it->second : make_dependent<T>( GetCore() )->GetCSRGetter( csr );
}

///< RevCSR: Get the custom setter for a particular CSR register
// If no custom setter exists for this RevCSR, look for one in the owning RevCore
template<typename CSR>
auto GetCSRSetter( CSR csr ) {
template<typename T = void>
auto GetCSRSetter( uint32_t csr ) {
auto it = Setter.find( csr );
return it != Setter.end() && it->second ? it->second : make_dependent<CSR>( GetCore() )->GetCSRSetter( csr );
return it != Setter.end() && it->second ? it->second : make_dependent<T>( GetCore() )->GetCSRSetter( csr );
}

/// Get the Floating-Point Rounding Mode
Expand All @@ -497,7 +497,10 @@ struct RevCSR : RevZicntr {

/// Get a CSR register
template<typename XLEN>
XLEN GetCSR( uint16_t csr ) const {
XLEN GetCSR( uint32_t csr ) const {
// Check for valid CSR register
if( csr >= 0x1000 )
fatal( "Invalid CSR register at PC = 0x%" PRIx64 "\n" );

// If a custom Getter exists, use it
auto getter = GetCSRGetter( make_dependent<XLEN>( csr ) );
Expand All @@ -507,9 +510,9 @@ struct RevCSR : RevZicntr {
// clang-format off
switch( csr ) {
// Floating Point flags
case fflags: return BitExtract<0, 5, XLEN>( CSR[fcsr] );
case frm: return BitExtract<5, 3, XLEN>( CSR[fcsr] );
case fcsr: return BitExtract<0, 8, XLEN>( CSR[fcsr] );
case fflags: return BitExtract<0, 5>( XLEN( CSR[fcsr] ) );
case frm: return BitExtract<5, 3>( XLEN( CSR[fcsr] ) );
case fcsr: return BitExtract<0, 8>( XLEN( CSR[fcsr] ) );

// Performance Counters
case cycle: return GetPerfCounter<XLEN, Half::Lo, rdcycle >();
Expand All @@ -527,7 +530,10 @@ struct RevCSR : RevZicntr {

/// Set a CSR register
template<typename XLEN>
bool SetCSR( uint16_t csr, XLEN val ) {
bool SetCSR( uint32_t csr, XLEN val ) {
// Check for valid CSR register
if( csr >= 0x1000 )
fatal( "Invalid CSR register at PC = 0x%" PRIx64 "\n" );

// Read-only CSRs cannot be written to
if( csr >= 0xc00 && csr < 0xe00 )
Expand All @@ -554,8 +560,8 @@ struct RevCSR : RevZicntr {

private:
std::array<uint64_t, CSR_LIMIT> CSR{}; ///< RegCSR: CSR registers
std::unordered_map<uint16_t, std::function<uint64_t( uint16_t )>> Getter{}; ///< RevCSR: CSR Getters
std::unordered_map<uint16_t, std::function<bool( uint16_t, uint64_t )>> Setter{}; ///< RevCSR: CSR Setters
std::unordered_map<uint32_t, std::function<uint64_t( uint32_t )>> Getter{}; ///< RevCSR: CSR Getters
std::unordered_map<uint32_t, std::function<bool( uint32_t, uint64_t )>> Setter{}; ///< RevCSR: CSR Setters

}; // class RevCSR

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22 changes: 11 additions & 11 deletions include/RevCore.h
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@@ -1,7 +1,7 @@
//
// _RevCore_h_
//
// Copyright (C) 2017-2024 Tactical Computing Laboratories, LLC
// Copyright (C) 2017-2025 Tactical Computing Laboratories, LLC
// All Rights Reserved
// [email protected]
//
Expand Down Expand Up @@ -278,30 +278,30 @@ class RevCore {
uint64_t GetCycles() const { return cycles; }

///< RevCore: Register a custom getter for a particular CSR register
void SetCSRGetter( uint16_t csr, std::function<uint64_t( uint16_t )> handler ) {
void SetCSRGetter( uint32_t csr, std::function<uint64_t( uint32_t )> handler ) {
handler ? (void) Getter.insert_or_assign( csr, std::move( handler ) ) : (void) Getter.erase( csr );
}

///< RevCore: Register a custom setter for a particular CSR register
void SetCSRSetter( uint16_t csr, std::function<bool( uint16_t, uint64_t )> handler ) {
void SetCSRSetter( uint32_t csr, std::function<bool( uint32_t, uint64_t )> handler ) {
handler ? (void) Setter.insert_or_assign( csr, std::move( handler ) ) : (void) Setter.erase( csr );
}

///< RevCore: Get the custom getter for a particular CSR register
auto GetCSRGetter( uint16_t csr ) const {
auto GetCSRGetter( uint32_t csr ) const {
auto it = Getter.find( csr );
return it != Getter.end() ? it->second : std::function<uint64_t( uint16_t )>{};
return it != Getter.end() ? it->second : std::function<uint64_t( uint32_t )>{};
}

///< RevCore: Get the custom setter for a particular CSR register
auto GetCSRSetter( uint16_t csr ) const {
auto GetCSRSetter( uint32_t csr ) const {
auto it = Setter.find( csr );
return it != Setter.end() ? it->second : std::function<bool( uint16_t, uint64_t )>{};
return it != Setter.end() ? it->second : std::function<bool( uint32_t, uint64_t )>{};
}

private:
std::unordered_map<uint16_t, std::function<uint64_t( uint16_t )>> Getter{};
std::unordered_map<uint16_t, std::function<bool( uint16_t, uint64_t )>> Setter{};
std::unordered_map<uint32_t, std::function<uint64_t( uint32_t )>> Getter{};
std::unordered_map<uint32_t, std::function<bool( uint32_t, uint64_t )>> Setter{};

bool Halted = false; ///< RevCore: determines if the core is halted
bool Stalled = false; ///< RevCore: determines if the core is stalled on instruction fetch
Expand Down Expand Up @@ -841,7 +841,7 @@ class RevCore {
}

/// RevCore: Check LS queue for outstanding load - ignore x0
static bool LSQCheck( uint32_t HartID, const RevRegFile* regFile, uint16_t reg, RevRegClass regClass ) {
static bool LSQCheck( uint32_t HartID, const RevRegFile* regFile, uint32_t reg, RevRegClass regClass ) {
if( reg == 0 && regClass == RevRegClass::RegGPR ) {
return false; // GPR x0 is not considered
} else {
Expand All @@ -850,7 +850,7 @@ class RevCore {
}

/// RevCore: Check scoreboard for a source register dependency
static bool ScoreboardCheck( const RevRegFile* regFile, uint16_t reg, RevRegClass regClass ) {
static bool ScoreboardCheck( const RevRegFile* regFile, uint32_t reg, RevRegClass regClass ) {
switch( regClass ) {
case RevRegClass::RegGPR: return reg != 0 && regFile->RV_Scoreboard[reg];
case RevRegClass::RegFLOAT: return regFile->FP_Scoreboard[reg];
Expand Down
4 changes: 2 additions & 2 deletions include/RevExt.h
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@@ -1,7 +1,7 @@
//
// _RevExt_h_
//
// Copyright (C) 2017-2024 Tactical Computing Laboratories, LLC
// Copyright (C) 2017-2025 Tactical Computing Laboratories, LLC
// All Rights Reserved
// [email protected]
//
Expand Down Expand Up @@ -55,7 +55,7 @@ struct RevExt {
std::string_view GetName() const { return name; }

/// RevExt: baseline execution function
bool Execute( uint32_t Inst, const RevInst& Payload, uint16_t HartID, RevRegFile* regFile ) const;
bool Execute( uint32_t Inst, const RevInst& Payload, uint32_t HartID, RevRegFile* regFile ) const;

/// RevExt: retrieves the extension's instruction table
const std::vector<RevInstEntry>& GetTable() const { return table; }
Expand Down
4 changes: 2 additions & 2 deletions include/RevFeature.h
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@@ -1,7 +1,7 @@
//
// _RevFeature_h_
//
// Copyright (C) 2017-2024 Tactical Computing Laboratories, LLC
// Copyright (C) 2017-2025 Tactical Computing Laboratories, LLC
// All Rights Reserved
// [email protected]
//
Expand Down Expand Up @@ -95,7 +95,7 @@ class RevFeature {
auto GetProcID() const { return ProcID; }

/// GetHartToExecID: Retrieve the current executing Hart
uint16_t GetHartToExecID() const { return HartToExecID; }
auto GetHartToExecID() const { return HartToExecID; }

/// SetHartToExecID: Set the current executing Hart
void SetHartToExecID( uint32_t hart ) { HartToExecID = hart; }
Expand Down
4 changes: 2 additions & 2 deletions include/RevHart.h
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@@ -1,7 +1,7 @@
//
// _RevHart_h_
//
// Copyright (C) 2017-2024 Tactical Computing Laboratories, LLC
// Copyright (C) 2017-2025 Tactical Computing Laboratories, LLC
// All Rights Reserved
// [email protected]
//
Expand Down Expand Up @@ -56,7 +56,7 @@ class RevHart {
const EcallState& GetEcallState() const { return Ecall; }

///< RevHart: Get Hart's ID
uint16_t GetID() const { return ID; }
uint32_t GetID() const { return ID; }

///< RevHart: Returns the ID of the assigned thread
uint32_t GetAssignedThreadID() const { return Thread ? Thread->GetID() : _INVALID_TID_; }
Expand Down
4 changes: 2 additions & 2 deletions include/RevInstHelpers.h
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@@ -1,7 +1,7 @@
//
// _RevInstHelpers_h_
//
// Copyright (C) 2017-2024 Tactical Computing Laboratories, LLC
// Copyright (C) 2017-2025 Tactical Computing Laboratories, LLC
// All Rights Reserved
// [email protected]
//
Expand Down Expand Up @@ -425,7 +425,7 @@ inline auto negate( T x ) {
// RISC-V requires INVALID exception when x * y is INVALID even when z = qNaN
template<typename T>
inline auto revFMA( T x, T y, T z ) {
if( ( !y && std::isinf( x ) ) || ( !x && std::isinf( y ) ) ) {
if( ( y == 0 && std::isinf( x ) ) || ( x == 0 && std::isinf( y ) ) ) {
feraiseexcept( FE_INVALID );
}
return std::fma( x, y, z );
Expand Down
17 changes: 9 additions & 8 deletions include/RevInstTable.h
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@@ -1,7 +1,7 @@
//
// _RevInstTable_h_
//
// Copyright (C) 2017-2024 Tactical Computing Laboratories, LLC
// Copyright (C) 2017-2025 Tactical Computing Laboratories, LLC
// All Rights Reserved
// [email protected]
//
Expand Down Expand Up @@ -89,11 +89,11 @@ class RevInst {
uint8_t funct4 = 0; ///< RevInst: compressed funct4 value
uint8_t funct6 = 0; ///< RevInst: compressed funct6 value
uint8_t funct2or7 = 0; ///< RevInst: uncompressed funct2 or funct7 value
uint64_t rd = ~uint64_t{}; ///< RevInst: rd value
uint64_t rs1 = ~uint64_t{}; ///< RevInst: rs1 value
uint64_t rs2 = ~uint64_t{}; ///< RevInst: rs2 value
uint64_t rs3 = ~uint64_t{}; ///< RevInst: rs3 value
uint64_t imm = 0; ///< RevInst: immediate value
uint32_t rd = ~uint32_t{}; ///< RevInst: rd value
uint32_t rs1 = ~uint32_t{}; ///< RevInst: rs1 value
uint32_t rs2 = ~uint32_t{}; ///< RevInst: rs2 value
uint32_t rs3 = ~uint32_t{}; ///< RevInst: rs3 value
uint32_t imm = 0; ///< RevInst: immediate value
bool raisefpe = 0; ///< RevInst: raises FP exceptions
FRMode rm{ FRMode::None }; ///< RevInst: floating point rounding mode
bool aq = false; ///< RevInst: aqr field for atomic instructions
Expand All @@ -110,11 +110,12 @@ class RevInst {
explicit RevInst() = default; // prevent aggregate initialization

///< RevInst: Sign-extended immediate value
constexpr int64_t ImmSignExt( int bits ) const { return SignExt( imm, bits ); }
constexpr auto ImmSignExt( int bits ) const { return SignExt( imm, bits ); }
}; // RevInst

/// CRegIdx: Maps the compressed index to normal index
constexpr auto CRegIdx( uint32_t x ) {
template<typename T>
constexpr auto CRegIdx( T x ) {
return x + 8;
}

Expand Down
4 changes: 2 additions & 2 deletions include/RevLoader.h
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@@ -1,7 +1,7 @@
//
// _RevLoader_h_
//
// Copyright (C) 2017-2024 Tactical Computing Laboratories, LLC
// Copyright (C) 2017-2025 Tactical Computing Laboratories, LLC
// All Rights Reserved
// [email protected]
//
Expand Down Expand Up @@ -349,7 +349,7 @@ class RevLoader {
bool LoadElf64( char* MemBuf, size_t Size );

///< Breaks bulk writes into cache lines
bool WriteCacheLine( uint64_t Addr, size_t Len, const void* Data );
bool WriteCacheLine( uint64_t Addr, uint32_t Len, const void* Data );

///< RevLoader: Replaces first MemSegment (initialized to entire memory space) with the static memory
void InitStaticMem();
Expand Down
12 changes: 6 additions & 6 deletions include/RevMem.h
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@@ -1,7 +1,7 @@
//
// _RevMem_h_
//
// Copyright (C) 2017-2024 Tactical Computing Laboratories, LLC
// Copyright (C) 2017-2025 Tactical Computing Laboratories, LLC
// All Rights Reserved
// [email protected]
//
Expand Down Expand Up @@ -167,10 +167,10 @@ class RevMem {
// ---- Base Memory Interfaces
// ----------------------------------------------------
/// RevMem: write to the target memory location with the target flags
bool WriteMem( uint32_t Hart, uint64_t Addr, size_t Len, const void* Data, RevFlag flags = RevFlag::F_NONE );
bool WriteMem( uint32_t Hart, uint64_t Addr, uint32_t Len, const void* Data, RevFlag flags = RevFlag::F_NONE );

/// RevMem: read data from the target memory location
bool ReadMem( uint32_t Hart, uint64_t Addr, size_t Len, void* Target, const MemReq& req, RevFlag flags = RevFlag::F_NONE );
bool ReadMem( uint32_t Hart, uint64_t Addr, uint32_t Len, void* Target, const MemReq& req, RevFlag flags = RevFlag::F_NONE );

/// RevMem: flush a cache line
bool FlushLine( uint32_t Hart, uint64_t Addr );
Expand All @@ -194,12 +194,12 @@ class RevMem {
void LR( uint32_t hart, uint64_t addr, size_t len, void* target, const MemReq& req, RevFlag flags );

/// RevMem: STORE CONDITIONAL memory interface
bool SC( uint32_t Hart, uint64_t addr, size_t len, void* data, RevFlag flags );
bool SC( uint32_t Hart, uint64_t addr, uint32_t len, void* data, RevFlag flags );

/// RevMem: template AMO memory interface
template<typename T>
bool AMOVal( uint32_t Hart, uint64_t Addr, T* Data, T* Target, const MemReq& req, RevFlag flags ) {
return AMOMem( Hart, Addr, sizeof( T ), Data, Target, req, flags );
return AMOMem( Hart, Addr, uint32_t{ sizeof( T ) }, Data, Target, req, flags );
}

// ----------------------------------------------------
Expand Down Expand Up @@ -228,7 +228,7 @@ class RevMem {
// ---- Atomic/Future/LRSC Interfaces
// ----------------------------------------------------
/// RevMem: Initiated an AMO request
bool AMOMem( uint32_t Hart, uint64_t Addr, size_t Len, void* Data, void* Target, const MemReq& req, RevFlag flags );
bool AMOMem( uint32_t Hart, uint64_t Addr, uint32_t Len, void* Data, void* Target, const MemReq& req, RevFlag flags );

/// RevMem: Invalidate Matching LR reservations
bool InvalidateLRReservations( uint32_t hart, uint64_t addr, size_t len );
Expand Down
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